Averaging FX2N-2AD Analog Input on FX1N PLC Integer Methods

Ryan Tanaka6 min read
FX SeriesMitsubishiTutorial / How-to
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Problem Overview

The Mitsubishi FX2N-2AD analog input module delivers two 12-bit channels into an FX1N CPU as 16-bit integer values in data registers. Field installations commonly see noise from thermocouples, RTD transmitters, 4-20 mA loops, and VFD-induced EMI on the analog cable. Engineers want to smooth the signal, but the FX1N family does not natively handle 32-bit REAL (floating-point) arithmetic the same way an FX3U or FX5U does. The FX1N programming manual (JY992D88101) section 4.15 documents FLOAT, not REAL, and ladder-instruction libraries such as DINC, DADD, and DMOV require careful data-type declaration to avoid the "type mismatched" compile error reported in the original PLCTalk thread.

Prerequisites

  • FX1N-14MR/MT or FX1N-24MR/MT CPU with firmware that supports the FROM/TO instructions
  • FX2N-2AD analog input module (catalog FX2N-2AD User's Manual, JY992D74701)
  • GX IEC Developer 7.04 or later, or GX Works 2 with FX1N compatibility mode
  • FX1N, FX1S, FX2N, FX2NC Programming Manual - JY992D88101
Critical: FX1N D registers are 16-bit. Any "32-bit" register pair such as D114/D115, D118/D119 occupies two consecutive addresses and must be declared as DOUBLE (signed 32-bit) in the IEC variable table before it can be passed into DADD, DMUL, or DDIV.

FX2N-2AD Hardware and Read Procedure

The FX2N-2AD occupies eight I/O points and identifies itself as a special-function block. Default number range is K0-K7, configurable by rotary switch. Average-mode and high-speed conversion are enabled by writing control word H0000 (normal) or H1000 (averaging) to buffer memory address 0 with the TO instruction, then read the digitized 12-bit value from buffer memory address 1 (CH1) and 2 (CH2) with the FROM instruction.

[ TO  K0  K0  H1100  K1 ]   ; enable averaging + 4-20 mA mode, BFM 0
[ FROM K0  K1  D100  K1 ]   ; read CH1 digital value (0-4000) into D100
[ FROM K0  K2  D102  K1 ]   ; read CH2 digital value into D102

Integer-Only Averaging Methods

Three approaches are practical on FX1N without breaking the integer data type. All three rely on the FX1N's integer math, and the choice depends on noise profile and available D-register budget.

Method 1: Hardware Averaging in the FX2N-2AD

The module's H1000 averaging bit samples 8 internally and returns the mean. No D register, no ladder scan overhead, no REAL required. The result is already integer in D100/D102. Use this first; it is the cleanest solution.

Method 2: Running Average (Single Register, Memory-Light)

The running-average formula A₁ = (I + (n-1) × A₀) / n requires only one previous-average register, not n samples. For n=16, the multiplier is 15. With D110 declared as DOUBLE for the previous average, the program becomes:

DADD D100 D114 D116       ; running_sum = I + A_prev*(n-1)  // D116 declared DOUBLE
DDIV D116 K16 D118        ; A_new = running_sum / 16
DMOV D118 D114            ; shift current average into "previous" slot

This technique is documented in the Industrial Monitor Direct knowledge base and scales well to FX1N's limited register budget.

Method 3: Sliding Window (N Samples)

For non-periodic spikes, a 16-deep circular buffer and integer mean is more accurate. Use a pointer in D200 and store raw samples in D300-D315. After 16 reads, copy the buffer to D320-D335 and apply a simple moving average. For larger N, indirect addressing with Z0/Z1 (index registers) is required; FX1N supports up to 16 index points in some firmware revisions, but Z0 is always present.

Fixing the "Type Mismatched" Compile Error

The error reported in the PLCTalk discussion occurs when 16-bit single-word variables are wired into 32-bit instructions. The fix sequence is:

  1. Open the Global Variable editor in GX IEC Developer.
  2. Locate D114, D116, D118, D120 and any other register feeding DADD, DMUL, DDIV, or DMOV.
  3. Change the data type from WORD to DWORD (DINT).
  4. For D100/D102 raw inputs being combined into a 32-bit sum, declare D100 explicitly as WORD but pre-merge with DMOV D100 D114 so the destination is DWORD.
  5. Rebuild the project. The type mismatch should clear.

If GX IEC Developer still rejects the project, switch the project's CPU target to FX1N (not FX1S) - FX1S has no 32-bit instructions, which is the most common root cause when developers attempt to use DADD on an FX1S.

Engineering Formulas for Filter Tuning

Filter performance in a control loop is measured against the analog scan period (T₀) of the FX2N-2AD, which is 15 ms per channel in high-speed mode or 6 ms with averaging disabled. The equivalent time constant τ of a running average of n samples is τ = (n-1) × T₀ / 2. For n=16 and T₀=15 ms, τ = 112 ms - fast enough for temperature, slow enough to reject 50/60 Hz pickup when combined with the module's own H1000 averaging.

Comparison: Smoothing Strategies

Method Registers Used FX1N-Compatible Noise Rejection Code Complexity
FX2N-2AD H1000 bit 0 Yes Moderate 1 rung
Running average (n=16) 2 double Yes (DWORD) High 4 rungs
Sliding window 16-deep 32 words Yes High 15+ rungs
Exponential filter 1 double Yes (DWORD) Tunable 3 rungs
REAL/FLOAT running n/a No native REAL Highest High

Verification Procedure

  1. Connect a precision 4-20 mA source (Yokogawa CA150 or similar) to CH1.
  2. Force the FX2N-2AD averaging bit OFF first; force a step change from 4 mA to 20 mA.
  3. Monitor D100 in GX Works 2 monitor mode. Confirm raw counts jump 0-4000 with visible noise of typically ±5 LSB.
  4. Enable Method 2 with n=8. Confirm the noise envelope drops to ±1 LSB while step response is acceptable for the controlled process.
  5. Repeat for CH2.
  6. Run the project for 24 hours with the process live; confirm no watchdog trip and D-register values remain within expected engineering range.
Note on FX1N-2DA (D/A) modules: The FX1N does support the FX2N-2DA (catalog JY992D74801) but only via FROM/TO and integer values. There is no requirement to use REAL numbers to write to a 2DA - integer counts 0-4000 produce 0-10 V or 4-20 mA directly. The original poster's question referenced the 2AD (input), not the 2DA (output).

FAQ

Does the FX1N support REAL numbers?

The FX1N does not implement IEEE-754 single-precision REAL natively. The programming manual (JY992D88101) section 4.15 documents a 32-bit FLOAT format and the FLOAT, FADD, FSUB, FMUL, FDIV, and FINT instructions, which behave as integer math with a fixed decimal offset. True 32-bit floating point (REAL/DINT conversion) is available on FX3U/FX3G and FX5U CPUs only.

How do I fix the "type mismatched" error on DADD or DMOV in GX IEC Developer?

Open the global variable table and change the data type of the destination register (for example D114, D116, D118) from WORD to DWORD/DINT. The 32-bit instructions DADD, DMOV, DDIV require a double-word destination; the source can remain a WORD if you pre-load it with DMOV first.

Can the FX2N-2AD average values for me?

Yes. Write H1000 to buffer memory 0 of the FX2N-2AD with the TO instruction to enable the module's internal averaging of 8 samples per channel. The integer result read back with FROM is already smoothed and requires no additional D-register arithmetic.

How many D registers are available for averaging on an FX1N?

The FX1N provides D0-D255 as general-purpose word registers (512 words with file-register expansion on some models). A 16-sample sliding window consumes 32 words; a running average consumes 2-4 double-words. Plan filter depth against the file-register ceiling when designing long rolling buffers.

Why use a running average instead of a sliding window on FX1N?

The running-average formula A = (I + (n-1) × A₀)/n uses a single previous-average register and scales of O(1) memory, freeing D-register space for the rest of the program. It is functionally equivalent to a first-order low-pass filter and is sufficient for the majority of temperature and pressure loops.

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