Building a Siemens S5/S7 Module Test Bench for Spare Verification

Building a Siemens S5/S7 Module Test Bench for Spare Verification

When a plant runs legacy SIMATIC S5 controllers alongside S7-300/S7-400 systems, the spare-parts inventory is often a mix of factory-new and refurbished (used) modules. Field engineers need a fast, repeatable method to confirm that a spare AI, AO, DI, DO, or CPU module is functional before installing it on a running machine. Hot-swapping modules on a live PLC rack is slow, risks wiring errors, and exposes production to unnecessary downtime. A dedicated test bench solves this problem by isolating module verification from the controlled process.

This reference covers a complete bench design for both SIMATIC S5 (S5-90U/95U/115U/135U/155U families) and SIMATIC S7-300/400 spares, including Report System Error (RSE) configuration in STEP 7, diagnostic buffer decoding, organization block (OB) fault codes, and pass/fail criteria. Procedures apply whether modules are pulled from a working machine, sourced from surplus stock, or salvaged from decommissioned racks.

1. Why Hot-Swapping Spare Modules Is the Wrong Approach

The naive workflow—stop equipment, stop PLC, disconnect one module at a time, rewire the spare, power up, test, restore—is both unsafe and inefficient on a production line:

• Downtime cost. Each cycle typically takes 20–45 minutes per module including wiring, restart, and verification.
• Wiring fatigue. Repeatedly disconnecting front connectors from terminals such as the 6ES5 730-... series front connectors breaks screw clamps and stranded-wire strands.
• Cross-contamination risk. A faulty spare installed next to a working module can propagate faults through the backplane, especially on S5-115U/135U/155U with EU (expansion unit) cabling.
• No diagnostic capture. Intermittent faults may pass when the spare is briefly installed but fail later in service. A controlled bench records the full diagnostic buffer.

A bench isolates the module under test, exercises every channel under load, and captures OB82/OB84/OB86/OB122 entries before the module is ever shipped to the field.

2. Prerequisites

Before building the test bench, confirm the following:

1. Working CPU. One fully functional CPU per family (S5-95U, S5-115U, S7-314, S7-414, etc.) acts as the master. Keep firmware versions consistent with the field fleet.
2. STEP 7 V5.5 SPx with SIMATIC Manager installed on a Windows 7 / XP / Windows 10 (compatibility mode) PC. The Report System Error wizard requires STEP 7 V5.3 or later.
3. PC Adapter USB (6ES7 972-0CB20-0XA0) or CP 5611 / CP 5613 MPI/Profibus card for S7-300/400.
4. PG 740 / PG 760 programmer or equivalent with S5-DOS / STEP 5 software for the S5 side.
5. Reference signal sources: 24 V DC bench supply (Phoenix Contact QUINT or Siemens SITOP), 0–10 V / 4–20 mA calibrator (Beamex MC6 or WIKA CPH7000), decade resistance box, and a 4-wire PT100 simulator.
6. Loads: 24 V lamp bank or programmable electronic load for DO verification, dummy transducers for AI channels.
7. Documentation: The Siemens S5-115U manual set (6ES5 998-0SH12 / -0SH22), the S7-300 Module Data manual, and the S7-400 Reference Manual.

3. Test Bench Architecture

The recommended topology separates S5 and S7 racks on independent frames but shares the 24 V DC supply and signal-conditioning block.

Figure 1 — Test bench topology with isolated S5 and S7 racks sharing a conditioned signal/load panel.

4. S5 Test Bench — Hardware and Test Points

4.1 Racks and Power

Use the original Siemens S5 racks:

• CR 700-0 (central rack) for S5-115U with up to 8 slots.
• ER 701-0 (expansion rack) connected via IM 306 / IM 308 for additional modules.
• PS 905 / PS 907 power supplies rated at 115/230 V AC input, 24 V DC / 5 V DC outputs.

4.2 Common S5 Spare Module Catalog Numbers

4.3 Wiring Convention

S5 front connectors are the 6ES5 730-... series with screw or cage-clamp terminals. Build pigtails that replicate field wiring: short jumper wires from a 24 V DC source through 1 kΩ resistors simulate field sensors for DI, while 24 V lamps with 470 Ω dropping resistors load the DO outputs.

5. S5 Verification Procedure

5.1 CPU Self-Test

1. Insert CPU with no EPROM/EEPROM initially. Power up — the BASP LED must light, and the CPU should request a memory reset (STOP mode with "REORG" if a memory card is inserted).
2. Insert EPROM/EEPROM with a known-good test program (FB-only OB1 echo: increment a counter and toggle an output on each scan).
3. Set the mode selector to RUN. The CPU must transition STOP → RUN within 3 seconds without triggering the SF (group fault) LED.
4. Read the diagnostic buffer via STEP 5 / COM 115/155. Acceptable entries: power-on, mode change, restart. Unacceptable: CPU fault, ISTACK overflow, module pull/plug during RUN when no module was removed.

5.2 Digital Input Modules

1. Apply 24 V DC to channel 0 via the front connector. The corresponding LED must light within 50 ms.
2. In STEP 5, monitor the process image input byte. Bit 0 must transition 0 → 1.
3. Cycle each channel with a debounced toggle switch. Verify both LED and process image.
4. For 110 V AC modules, use an isolated variac — never connect bench mains directly to module terminals without an isolation transformer.

5.3 Digital Output Modules

1. Drive each output high via the test program. Verify the channel LED and measure voltage at the load terminal (should drop ≤ 0.5 V at rated load).
2. Apply a 10 % over-current condition (e.g., 0.55 A on a 0.5 A module) for 60 s. The module must fold back or trip the group fuse without latching the CPU into STOP.
3. For relay modules, exercise each contact with an ohm-meter: closed resistance < 100 mΩ, open resistance > 100 MΩ.

5.4 Analog Input Modules

1. Apply 0 V, 5 V, and 10 V from the calibrator to channels 0–7.
2. Read the raw value from the process image. For a 12-bit bipolar module the expected linear mapping is:

Value = (Vin / 10 V) * 2048 + 2048
Example: Vin = +5.000 V -> Value = 1024 + 2048 = 3072 decimal (0xC00)
Example: Vin = -10.000 V -> Value = -2048 + 2048 = 0 (under-range clamp)

3. Acceptance: every channel within ±2 LSB of expected at all three test points. Reject if any channel drifts > 4 LSB over 5 minutes.
4. For RTD modules (6ES5 465), verify linearity at 0 °C, 100 °C, and 200 °C with PT100 simulator.

5.5 Analog Output Modules

1. Set each channel to 0 %, 50 %, 100 % from the test program.
2. Measure with a 6½-digit DMM at the front connector.
3. Acceptance: ±0.3 % of full scale (typical Siemens 12-bit AO spec).

6. S7 Test Bench — Report System Error Setup

The S7-300/S7-400 side uses the STEP 7 "Report System Error" (RSE) wizard to generate automatic diagnostics. Once configured, the CPU writes diagnostic messages to the diagnostic buffer and to DB 125 (S7-300) or DB 126 (S7-400), where they can be retrieved from the HMI or engineering station.

6.1 Configuration Steps in SIMATIC Manager

1. Open HW Config for the bench station.
2. Insert the CPU (e.g., 6ES7 314-6CG03-0AB0) and add all slave modules that will be exercised (SM 321, SM 322, SM 331, SM 332).
3. Select the CPU row, then choose Options → Report System Error.
4. In the wizard, enable diagnostics for:

CPU diagnostics              : YES
OB82 (diagnostic interrupt)  : YES (used)
OB83 (module pull/plug)      : YES (used)
OB84 (CPU/IM failure)        : YES (used)
OB85 (OB not loaded)         : YES (used)
OB86 (rack failure)          : YES (used)
OB121 (programming error)    : YES (used)
OB122 (I/O access error)     : YES (used)
Generate DB 125 / DB 126     : YES
Send to HMI / WinCC          : optional

5. Compile and download to the CPU. RSE installs OB82, OB83, OB84, OB85, OB86, OB121, OB122 (these are now present in the S7 program).
6. Open CPU Messages via PLC → CPU Messages. Faulty modules will surface here with event IDs.

6.2 Diagnostic Buffer Readout

After each module test cycle, perform PLC → Diagnostics/Settings → Clear/Reset Diagnostic Buffer only if desired, then run the test and read the buffer in chronological order. Key event IDs for module faults:

7. Organization Block (OB) Fault Reference

The OB priority and reaction table is essential for interpreting diagnostic buffer entries.

8. Pass/Fail Decision Matrix

9. Commissioning Verification Steps

Run this checklist every time the bench is re-cabled or a new CPU firmware is installed:

1. Confirm the SITOP PSU voltage is 24.0 V ±0.2 V DC under load.
2. Confirm the calibrator has been calibrated within the last 12 months (NIST or accredited lab traceable).
3. Power the rack with no module under test — CPU must complete power-on self-test within 5 s and reach RUN on a clean test FB.
4. Insert a known-good reference module (kept on the bench as a golden unit). Confirm all tests pass.
5. Insert the spare module and run the full test sequence.
6. Save the diagnostic buffer and a screenshot of HW Config showing the module present in green.
7. Tag the module with a barcode label: PASS / FAIL, date, technician initials, firmware version.

10. Troubleshooting Common Bench Issues

11. Documentation and Records

Maintain a CSV or relational log per spare:

Module_MLFB,Serial_No,Family,Firmware,Test_Date,Technician,Pass_Fail,Notes
6ES7 322-1BL00-0AA0,S730-2204-AK08,S7-300 DO16,FW V3.0,2026-01-14,JD,PASS,Channel 12 within 1 LSB
6ES5 460-4UA12,S540-0612-118,S5-115U AI8,n/a,2026-01-14,JD,FAIL,Channel 3 reads 8 LSB high
6ES7 314-6CG03-0AB0,S7314-AK21-0928,S7-300 CPU314C-2,FW V3.3,2026-01-14,JD,PASS,Clean OB82 after 24h burn-in

This log feeds the inventory system and provides evidence during quality audits for ISO 9001 or equivalent quality management systems.

12. References in Procedure

• Siemens SIMATIC S5-115U Manual Set (6ES5 998-0SH12)
• S7-300 Module Data (manual collection)
• STEP 7 V5.5 Report System Error — function manual
• S7-300 CPU 31xC and CPU 31x — Operating Instructions