Configuring 1SI 5V/500kHz Counter Module on S7-300 ET 200S

David Krause19 min read
I/O ModulesSiemensTutorial / How-to
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Module Identification and System Architecture

The Siemens 1SI 5V/500kHz counter module (MLFB 6ES7 138-4DE02-0AB0) is a single-channel incremental encoder/counter module designed for the ET 200S distributed I/O system. It accepts 5V TTL differential (RS-422) pulse trains at input frequencies up to 500 kHz, evaluates the A/B quadrature signals, and returns a 32-bit count value, status flags, and a hardware gate state to the host PLC. The module is the standard choice when the encoder signal is 5V TTL and the application requires high count rates, precise position capture, or direct load-signal evaluation.

Within an ET 200S station, the 1SI 5V/500kHz electronics module must be inserted into a TM-E 30S terminal module family. The variant TM-E 30S-44-01 (6ES7 193-4CG40-0AA0) provides the 30 mm wide screw-type terminals and the internal wiring path that maps the encoder signals (A, /A, B, /B, N, /N, 24V encoder supply) to the front connector of the electronics module. The terminal module is the only piece of the station that physically exposes the encoder lines; the electronics module itself is replaced during service without re-wiring.

For an S7-300 station based on a CPU 315-2PN/DP (MLFB 6ES7 315-2EH14-0AB0), the ET 200S head-end is selected according to the fieldbus used:

  • PROFIBUS DP — IM 151-1 STANDARD (6ES7 151-1AA05-0AB0) or IM 151-1 HF (6ES7 151-1BA02-0AB0)
  • PROFINET — IM 151-3PN HF (6ES7 151-3BA23-0AB0) for 1SI 5V/500kHz, since the standard IM 151-3PN does not support 1SI modules

The IM 151-3PN HF is required because the 1SI 5V/500kHz uses the technological-functions record set that is only available on HF interface modules. A CPU 315-2PN/DP host on PROFINET integrates the ET 200S station through a standard GSD file (GSDML-Vx.x-Siemens-ET200S-xxxxxxxx.xml) imported into the device catalog.

Technical Specifications of 1SI 5V/500kHz

The following electrical and functional data are taken from the Siemens "ET 200S Technological Functions" manual, which lists this module under part number 6ES7 138-4DE02-0AB0.

1SI 5V/500kHz (6ES7 138-4DE02-0AB0) key specifications
Parameter Value
Number of channels 1
Signal level, encoder inputs (A, /A, B, /B, N, /N) 5V TTL differential per RS-422
Maximum input frequency 500 kHz (quadrature 4× = 2 MHz edge count)
Counter width 32 bits (±31 bits, signed)
Encoder supply output 24V DC, max. 300 mA, short-circuit-proof
Galvanic isolation 500V AC (encoder to backplane)
DIAG status Wire break, signal level error, encoder supply overload, gate error
Operating modes Continuous counting, single counting, periodic counting, frequency measurement, rotation-speed measurement
Comparison values 2 hardware comparators (DQ0, DQ1 outputs mapped to PQW)
Gate control Software gate (via PQW) and hardware gate (via DI of TM-E)
Power consumption from backplane Approx. 0.6 W
Critical wiring constraint: The 24V encoder supply is provided on the TM-E 30S-44-01, but the A/B/N signal lines must be 5V TTL differential. The most frequent installation error is to wire a 24V HTL encoder directly to the encoder inputs; the resulting high-level voltage exceeds the 5V specification and produces a wire-break diagnostic without a count increment. Use a 5V TTL encoder or a level converter (e.g., Siemens 6ES7 138-4DA00-0AB0 type, or a third-party HTL-to-TTL converter).

Prerequisites

Before commissioning the counter module, verify the following:

  1. STEP 7 V5.5 SP4+ (Classic) or TIA Portal V13+ — Both support the 1SI 5V/500kHz via the HSP (Hardware Support Package) GSD files. In STEP 7 Classic, install HSP "ET200S_AI_AO_DI_DO_1SI" or the cumulative HSP for the 138-4DE02 module.
  2. GSD/GSDML file — Import the matching GSDML for the IM 151-3PN HF and the 1SI 5V/500kHz sub-module into the device catalog.
  3. IM 151-3PN HF — Required for PROFINET integration with the 1SI 5V/500kHz, since the standard IM 151-3PN does not support the technological-functions record set.
  4. 5V TTL encoder — The encoder must be a true 5V differential (RS-422) output device, not a 24V HTL push-pull device. Confirm via encoder datasheet that the high-level output voltage is between 2.0V and 5.5V and that the line driver is RS-422 compatible (e.g., 26LS31, AM26C31).
  5. Shielded twisted-pair cable — Use a shielded twisted-pair cable with one pair per channel (A/̄Ā, B/̄B̄, N/̄N̄) and connect the shield to the functional earth terminal of the TM-E 30S-44-01 at the cabinet entry only.
  6. PROFINET/PROFIBUS configuration tool — For the CPU 315-2PN/DP, use either SIMATIC Manager (STEP 7 V5.5) or TIA Portal. The article below covers STEP 7 Classic first and notes the TIA Portal differences at the end.

Hardware Configuration in STEP 7 (HW Config)

  1. Open the S7 project in SIMATIC Manager and launch HW Config.
  2. Insert the CPU 315-2PN/DP (6ES7 315-2EH14-0AB0) into slot 2 of the S7-300 rack.
  3. Open the PROFINET subnet on the CPU and drag the IM 151-3PN HF (6ES7 151-3BA23-0AB0) onto the subnet. Assign a PROFINET device name (e.g., "et200s-cntr1") and an IP address in the same subnet as the CPU.
  4. In the IM 151-3PN HF slot table, insert the 1SI 5V/500kHz module (6ES7 138-4DE02-0AB0) at the next free slot. The slot is automatically mapped to a TM-E 30S-44-01 terminal module.
  5. Double-click the 1SI module to open its properties. Configure the following parameters:
    • Operating mode: "Continuous counting up/down" for an A/B encoder with direction discrimination
    • Signal evaluation: "4-fold evaluation" (quadrature 4×) for maximum resolution
    • Counter range: −2,147,483,648 to 2,147,483,647 (32-bit signed)
    • Hardware gate: "interrupted, cancels the count" or "interrupted, stops the count" depending on application
    • Software gate: "Cancel with "0"" (default)
    • Encoder monitoring: enable wire break and signal-level diagnostics
    • Comparator DQ0 / DQ1: enable and assign comparison value via control interface
  6. Click "OK" and download the HW Config to the CPU. The configured I/O addresses are displayed in the slot table — for example, inputs starting at PIW 288 and outputs starting at PQW 288. Note these addresses for the user program.

TM-E 30S-44-01 Terminal Assignment

The terminal module exposes the following screw terminals. The pinout below is the standard mapping for the 1SI 5V/500kHz electronics module; always verify against the wiring diagram printed inside the terminal module door before commissioning.

TM-E 30S-44-01 terminal assignment for 1SI 5V/500kHz
Terminal Signal Function
1 A Encoder track A, true (5V TTL)
2 Encoder track A, inverted (5V TTL)
3 B Encoder track B, true (5V TTL)
4 Encoder track B, inverted (5V TTL)
5 N Encoder zero pulse, true (5V TTL)
6 Encoder zero pulse, inverted (5V TTL)
7 24V Encoder power supply + (24V DC, max. 300 mA)
8 0V Encoder power supply − (24V DC return)
9 DI Hardware gate input (24V DC input)
10 M Reference ground for DI
11 DQ0 Digital output 0 / Comparator 0 (24V DC, 0.5 A)
12 DQ1 Digital output 1 / Comparator 1 (24V DC, 0.5 A)
13 FE Functional earth — connect encoder cable shield here
14 n.c. Reserved
Twisted-pair pairing: A/̄Ā, B/̄B̄, and N/̄N̄ must each be on a twisted pair. Do not run A and B on the same pair; doing so destroys the noise immunity of the differential receiver and causes random direction reversals at high count rates.

For the support entry describing the wiring diagram and an example project, refer to the Siemens support article ID 45977588 in the Siemens Industry Online Support portal. The example project demonstrates the IM 151-3PN configuration and a sample STEP 7 program for the 1SI 5V/500kHz module.

Encoder Signal Level Considerations

The 1SI 5V/500kHz module is unusual in the Siemens product line because most ET 200S counter modules (1SI 24V/100kHz, 1COUNT 24V/100kHz, 1SSI) accept 24V signals. The 5V variant is purpose-built for high-frequency applications where 5V TTL encoders are still common — typically small incremental encoders with resolutions above 5,000 ppr (pulses per revolution) running at shaft speeds that push the input frequency above 100 kHz.

The 5V TTL encoder inputs accept a true differential RS-422 signal with the following threshold limits:

  • VIH (differential high) ≥ 200 mV
  • VIL (differential low) ≤ −200 mV
  • Common-mode input range ±7V

A 24V HTL encoder output (typical high level: 22 to 26V) will fail the VIH/VIL thresholds and the module reports a wire break. The recommended solutions are:

  1. Use a true 5V TTL encoder — common in the 1,000–10,000 ppr range with 5V supply from the module. Manufacturers: Hohner, Kübler, Baumer, Sick, Heidenhain (E-series with TTL option).
  2. Use a 24V-to-5V level converter — Siemens does not sell a dedicated HTL-to-TTL converter for ET 200S. Third-party modules (e.g., Phoenix Contact MINI MCR-2-UI-REL or Wieland TTL converter) are used; verify the converter bandwidth is at least 10× the maximum input frequency to preserve edge fidelity at 500 kHz.
  3. Use a 24V counter module instead — 1SI 24V/100kHz (6ES7 138-4DE11-0AB0) or 1COUNT 24V/100kHz (6ES7 138-4DL00-0AB0). The frequency limit drops to 100 kHz, which is sufficient for many applications.
Open-collector encoders require a pull-up resistor to 5V at the receiver end. The 1SI 5V/500kHz does not provide internal pull-ups; for open-collector 5V encoders, add an external 1 kΩ pull-up to the +5V supply, but note that the encoder supply terminal on the TM-E is 24V, not 5V. Provide a separate 5V source if a 5V pull-up is required.

Operating Modes

The 1SI 5V/500kHz supports four primary operating modes, selected in HW Config:

Operating modes of 1SI 5V/500kHz
Mode Use case Behavior
Continuous counting, up/down Position tracking with direction-sensing A/B encoder Counter increments on A leading B, decrements on B leading A. Range wraps at ±2,147,483,647. Gate and zero pulse control the count.
Single counting Event counting with a defined start/stop Counter starts on SW gate open, stops on SW gate close or HW gate close, returns the count.
Periodic counting Length measurement with automatic reset on zero pulse Counter resets to load value on each N pulse. Used for axis positioning on a single turn.
Frequency / speed measurement RPM or line-speed display Module counts pulses over a fixed integration time and reports the frequency in 0.01 Hz resolution.

For position-control applications with a single A/B encoder, "Continuous counting, up/down" with 4-fold evaluation gives the maximum resolution (4 × pulses-per-revolution counts per shaft turn).

Address Map and I/O Access

The 1SI 5V/500kHz occupies 8 bytes of input and 8 bytes of output process image. The default base addresses depend on the slot and the IM 151-3PN HF configuration. A typical mapping (PROFINET slot 1) is:

Default I/O mapping for 1SI 5V/500kHz at slot 1 (PROFINET)
Address Type Function
PIW 288 Input word 0 Status word (STS) — see decoding below
PIW 290 Input word 1 Reserved / extended status
PID 292 Input double word Current count value (32-bit signed)
PQW 288 Output word 0 Control word (CTRL) — gate, load, set, reset
PQW 290 Output word 1 Reserved
PQD 292 Output double word Load value (32-bit) for set counter

The status word (PIW 288) is decoded as follows:

Status word bit assignment (PIW 288)
Bit Symbol Meaning
0 STS_GATE Internal gate open (1 = counting)
1 STS_DIR Direction: 1 = count up, 0 = count down
2 STS_CMP0 Comparator 0 reached
3 STS_CMP1 Comparator 1 reached
4 STS_N Zero pulse (N) seen since last reset
5 STS_RES Reserved
6 STS_LATCH Latch function active
7 STS_DIAG Diagnostic pending (see DIAG byte)
8–15 Reserved / extended status

The control word (PQW 288) is decoded as:

Control word bit assignment (PQD 288)
Bit Symbol Meaning
0 CTRL_SW_GATE 1 = open software gate, 0 = close
1 CTRL_SET 1 = load value from PQD 292 into counter (rising edge)
2 CTRL_RES Reserved / not used for 1SI 5V/500kHz
3 CTRL_CMP0_EN 1 = enable comparator 0
4 CTRL_CMP1_EN 1 = enable comparator 1
5–7 Reserved
8 CTRL_CMP0_ACK 1 = acknowledge comparator 0 output
9 CTRL_CMP1_ACK 1 = acknowledge comparator 1 output
10–15 Reserved

Sample Program — Up/Down Counting on S7-300 (STEP 7 Classic, STL)

The following sample is taken from the "ET 200S Technological Functions" manual (page 121 and following) and adapted to a standalone OB1 cycle without the higher-level FCs from the Siemens library. It is the minimum program required to:

  1. Open the software gate
  2. Read the current count and direction
  3. Set the counter to a load value (e.g., 0) on a button press
  4. Acknowledge the comparator outputs

Data block DB100 layout:

DATA_BLOCK DB100
  STRUCT
    iCount   : DINT ; // current count (copy of PID 292)
    iStatus  : WORD ; // copy of PIW 288
    iLoadVal : DINT ; // load value = 0
    bGate    : BOOL ; // software gate request
    bSetZero : BOOL ; // "Set to zero" pushbutton
    bCmp0Ack : BOOL ; // comparator 0 acknowledge
    bCmp1Ack : BOOL ; // comparator 1 acknowledge
    bDir     : BOOL ; // up/down direction (TRUE = up)
    bRunning : BOOL ; // gate open flag
  END_STRUCT
END_DATA_BLOCK

OB1 — main cyclic program (STL, comments inline):

// ----- READ INPUTS -----
L     PIW 288            // status word
T     DB100.DBW  2       // DB100.iStatus
L     PID 292            // 32-bit count value
T     DB100.DBD  0       // DB100.iCount

// ----- DECODE DIRECTION -----
A     DB100.DBX   3.1    // STS_DIR bit (bit 1 of status word)
=     DB100.DBX  12.0    // DB100.bDir

// ----- SOFTWARE GATE HANDLING -----
A     DB100.DBX   8.0    // DB100.bGate from HMI / logic
=     Q 288.0            // CTRL_SW_GATE bit (bit 0 of PQW 288)

// ----- SET COUNTER TO LOAD VALUE ON REQUEST -----
A     DB100.DBX   8.1    // DB100.bSetZero (pushbutton)
FP                         // rising-edge detect
S     Q 288.1            // CTRL_SET bit (bit 1 of PQW 288)
A     DB100.DBX   8.1
FN                         // falling-edge detect
R     Q 288.1            // release CTRL_SET

// ----- WRITE LOAD VALUE -----
L     DB100.DBD  12      // DB100.iLoadVal
T     PQD 292            // load value (32-bit)

// ----- COMPARATOR ACKNOWLEDGE -----
A     DB100.DBX   8.2    // DB100.bCmp0Ack
S     Q 288.8            // CTRL_CMP0_ACK (bit 8 of PQW 288)
A     DB100.DBX   8.2
R     Q 288.8

A     DB100.DBX   8.3    // DB100.bCmp1Ack
S     Q 288.9            // CTRL_CMP1_ACK (bit 9 of PQW 288)
A     DB100.DBX   8.3
R     Q 288.9

The same program in TIA Portal SCL is shorter and easier to maintain:

// Counter: 1SI 5V/500kHz, slot 1, base address 288
// Hardware identifier (HW ID) is read from the device configuration
// 'hwCnt' is the HW ID of the 1SI module

// 1. Read process image (PI service is implicit in TIA Portal)
iStatus  := "CNT_IN".STS;        // alias for PQW 288 input area
iCount   := "CNT_IN".COUNT;     // alias for PID 292

// 2. Decode direction
bDir := (iStatus AND 16#0002) <> 0;   // bit 1 = STS_DIR

// 3. Open software gate
IF bGateRequest THEN
    "CNT_OUT".CTRL := "CNT_OUT".CTRL OR 16#0001;   // CTRL_SW_GATE
ELSE
    "CNT_OUT".CTRL := "CNT_OUT".CTRL AND 16#FFFE;
END_IF;

// 4. Set counter to load value on rising edge
IF bSetZero AND NOT bSetZeroOld THEN
    "CNT_OUT".CTRL := "CNT_OUT".CTRL OR 16#0002;   // CTRL_SET
ELSE
    "CNT_OUT".CTRL := "CNT_OUT".CTRL AND 16#FFFD;
END_IF;
bSetZeroOld := bSetZero;

// 5. Write load value
"CNT_OUT".LOAD := iLoadVal;          // 32-bit DINT

// 6. Comparator acknowledge
IF bCmp0Ack THEN
    "CNT_OUT".CTRL := "CNT_OUT".CTRL OR 16#0100;   // bit 8
ELSE
    "CNT_OUT".CTRL := "CNT_OUT".CTRL AND 16#FEFF;
END_IF;
Bit ordering: In STEP 7 Classic, the control word is written with bit 0 = SW gate, bit 1 = SET, bit 8 = CMP0 ack, bit 9 = CMP1 ack. In TIA Portal the process image exposes the same bits through the symbolic alias "CNT_IN".STS and "CNT_OUT".CTRL; the bit positions do not change. Do not invert the bit positions when migrating code between V5.5 and TIA Portal — the assignment is identical.

Comparator Configuration for Up/Down Position Control

To use the hardware comparators for position control, the comparison value is written to a separate I/O range, not the load value range. The address for the comparator setpoint depends on the slot. The typical layout on PROFINET slot 1 is:

Comparator setpoint addresses (PROFINET slot 1)
Address Type Function
PQD 296 Output double word Comparison value for comparator 0 (DINT)
PQD 300 Output double word Comparison value for comparator 1 (DINT)

The comparator mode is configured in HW Config (Properties → 1SI module → Comparator). For a position switch (e.g., "position reached at 5,000 counts"), enable the comparator in "Single" mode and load the setpoint:

L     5000
T     PQD 296            // comparator 0 setpoint
SET
=     Q 288.3            // CTRL_CMP0_EN (bit 3 of PQW 288)
R     Q 288.3

When the counter reaches 5,000, STS_CMP0 (bit 2 of PIW 288) is set, the corresponding digital output DQ0 (terminal 11) switches high, and the STS_CMP0 bit stays set until the user program writes CTRL_CMP0_ACK (bit 8) high to acknowledge.

Commissioning and Verification

  1. Power the ET 200S station. The IM 151-3PN HF BUS-FAULT LED should be off and the RUN LED on the CPU should be steady green.
  2. From the STEP 7 / TIA Portal online view, force Q 288.0 = 1 (open software gate). The status word PIW 288 bit 0 (STS_GATE) should change to 1 within one DP/PN cycle.
  3. Connect an oscilloscope or signal generator to terminals 1/2 of the TM-E 30S-44-01 and inject a 5V TTL square wave at 1 kHz on track A only (terminals 1 and 2, differential). The count value (PID 292) should increment at 1,000 counts per second.
  4. Inject a 1 kHz quadrature signal (A leading B) on terminals 1/2 and 3/4. The count should still increment; the direction bit (PIW 288 bit 1) should read 1. Reverse B (swap terminals 3 and 4) and the direction bit should read 0 while the count decrements.
  5. Inject a 500 kHz signal at the rated amplitude. The count should follow with a 4× evaluation (4,000 counts per mechanical pulse). If the count skips, the cable is too long or the encoder is bandwidth-limited; shorten the cable or check the encoder datasheet.
  6. Trigger a wire break by disconnecting the /A line (terminal 2). The DIAG LED on the module should flash red and STS_DIAG (PIW 288 bit 7) should go high. Reconnect and the diagnostic clears on the next PN cycle.
  7. Toggle the hardware gate (terminal 9 to 24V) and verify the count freezes. The hardware gate has higher priority than the software gate.

Troubleshooting Matrix

Common faults and remedies for 1SI 5V/500kHz (6ES7 138-4DE02-0AB0)
Symptom Likely cause Diagnostic step Remedy
Count does not increment; DIAG LED red 24V encoder wired to 5V input Measure VAB (A vs /A) with scope. If > 5V, signal is HTL Replace encoder with 5V TTL unit, or add a level converter
Count increments, direction wrong A and B swapped, or /A and /B swapped Swap A and B on TM-E 1/3 and verify direction bit Swap the A/̄Ā or B/̄B̄ pair on the TM-E
STS_GATE = 0 even with Q 288.0 = 1 Hardware gate open (terminal 9) is at 0V or floating Measure terminal 9 against 10 Drive terminal 9 to 24V (hardware gate = 1)
Count overshoots expected value 4× evaluation enabled but encoder is single-channel Check encoder datasheet for A only or A/B Set signal evaluation to "single" or "2×"
Count skips at high frequency Cable too long, no twisted pair, or wrong shield Verify cable ≤ 50 m for 500 kHz, twisted pair per channel Re-pull cable with twisted pair, ground shield at one end
Comparator output DQ0 does not switch Comparator disabled in HW Config Check CTRL_CMP0_EN (Q 288.3) Set bit 3 in HW Config and load setpoint
STS_DIAG high after startup Encoder supply overload (> 300 mA) Measure encoder current draw Use external 24V supply for the encoder
Module not detected on PROFINET IM 151-3PN standard, not HF Read IM 151-3PN order code; check part number Replace with IM 151-3PN HF (6ES7 151-3BA23-0AB0)
Cross-reference for similar modules: For an Allen-Bradley POINT I/O encoder/counter application at 5V (e.g., the 1734-IJ), refer to the 1734-UM006B POINT I/O Encoder/Counter Modules User Manual for the equivalent 5V input specifications, count rollover, and preset configuration. The Siemens 1SI 5V/500kHz behaves similarly with respect to preset, rollover, and count-value latching, but uses the ET 200S I/O address mapping and the STS / CTRL bit layout described above.

Differences in TIA Portal

For projects migrated to TIA Portal V13 or later, the configuration steps are equivalent but the UI differences are:

  1. The 1SI module is added from the device catalog under "ET 200S → IM 151-3PN HF → Counter → 1SI 5V/500kHz".
  2. Process image names (e.g., "CNT_IN", "CNT_OUT") are defined in the PLC tags and are symbolic — the absolute address (PIW 288) is shown on the right of the tag editor for cross-reference.
  3. The hardware identifier (HW ID) is used by the I/O read/write blocks (e.g., RDREC, WRREC for record-set access to comparator configuration). TIA Portal generates the HW ID automatically.
  4. The Technological Functions library (FC "CNTR_1SI") is included from "Options → Support Packages → SIMATIC ET 200S Tech Functions" if a higher-level FC interface is required.

Safety and Maintenance Notes

  • Disconnect the ET 200S station power before replacing the 1SI electronics module. The module can be hot-swapped only when the IM 151 interface module and the station configuration explicitly support module replacement in RUN (CiR); the standard ET 200S configuration requires a STOP state for module exchange.
  • After replacement, the 1SI 5V/500kHz returns the count to zero unless the load value is re-written by the user program. Include the load-value write in OB100 (restart) or OB1 to ensure deterministic position recovery after a module swap.
  • The encoder cable shield must be terminated at the TM-E functional earth terminal (terminal 13) using a short pigtail (≤ 50 mm) to avoid pigtail-induced EMI at 500 kHz.
  • Do not route the encoder cable parallel to VFD output cables or to DC high-current busbars. A separation of at least 200 mm, or a metal divider, is recommended for 5V TTL signals at 500 kHz.

FAQ

What is the MLFB of the 1SI 5V/500kHz counter module and what terminal module does it require?

The electronics module is MLFB 6ES7 138-4DE02-0AB0. It requires a TM-E 30S-44-01 screw-type terminal module (MLFB 6ES7 193-4CG40-0AA0) which routes the 5V TTL encoder signals, the 24V encoder supply, and the hardware gate DI to the electronics module front connector.

Why are 5V TTL encoders hard to find, and can I use a 24V encoder with the 1SI 5V/500kHz?

Most incremental encoders sold today are 24V HTL. A 24V HTL encoder wired directly to the 5V TTL inputs of the 1SI will exceed the VIH/VIL thresholds and the module reports a wire break. Use a 5V TTL encoder (Hohner, Kübler, Baumer, Sick) or add a third-party HTL-to-TTL level converter with at least 10× the maximum input frequency bandwidth.

Which IM 151 interface module is required for PROFINET integration of the 1SI 5V/500kHz?

Use the IM 151-3PN HF (MLFB 6ES7 151-3BA23-0AB0). The standard IM 151-3PN does not support the technological-functions record set used by the 1SI 5V/500kHz. For PROFIBUS DP, the IM 151-1 STANDARD (6ES7 151-1AA05-0AB0) is sufficient.

How do I open the software gate and read the current count in STEP 7?

Write 1 to Q 288.0 (bit 0 of PQW 288) to open the software gate. Read PID 292 (32-bit signed DINT) for the count value and PIW 288 for the status word. STS_GATE (bit 0 of PIW 288) returns 1 when the internal gate is open and the counter is integrating.

What is the maximum count rate of the 1SI 5V/500kHz in 4× evaluation?

The maximum input frequency is 500 kHz on the A/B pulse trains. With 4× (quadrature) evaluation, the counter increments at 2,000,000 edges per second. The count value is a 32-bit signed integer (±2,147,483,647) and rolls over automatically.

Where can I find the official Siemens example project for the 1SI 5V/500kHz?

The "ET 200S Technological Functions" manual (page 121 and following) provides a sample program for up/down counting and comparator configuration. Siemens Industry Online Support entry ID 45977588 includes a downloadable example project with HW Config and STEP 7 V5.5 sources.

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