Configuring CompactLogix Shift Timing Below 1 ms Guide

On the programming panel, the timer preset accepts 100 ms or 101 ms, but it cannot represent 100.2 ms or 100.9 ms. CompactLogix timer presets use a 1 ms timebase and store .PRE and .ACC as double integers. Use alternating whole-millisecond presets only when you need a long-term average; use position feedback, a dedicated timing module, or motion control when each shift must occur with sub-millisecond precision.

Read the symptom before changing logic

Start here. Define what the process actually needs:

• Average rate: The shift register must average one shift every 100.2 ms or 100.9 ms over many cycles.
• Maximum interval error: Every shift must occur within a stated tolerance of its scheduled time.
• Position accuracy: Each bit must follow conveyor travel or the physical location of an object.

Those are different control problems. Alternating 100 ms and 101 ms presets can satisfy an average-rate requirement. It does not make either interval fractional, remove task-scheduling jitter, or prove that the modeled bit position matches the machine.

Also check how the BSL instruction is triggered. A level that remains true across multiple task executions can shift more than once. Feed the instruction a rising-edge event or a one-execution pulse so one timer completion produces one shift.

Understand the 1 ms storage limit

The ControlLogix-family timer timebase is 1 millisecond. The timer tag's .PRE and .ACC members are double integers, so the built-in timer represents whole milliseconds:

• 100 represents 100 ms.
• 101 represents 101 ms.
• 100.2 has no fractional field in which to store the final 0.2 ms.

Changing from a nonretentive TON to an RTO does not change that resolution. Retention changes what happens to accumulated time when the instruction is disabled; it does not create a fractional-millisecond preset.

A numeric conversion around the instruction cannot recover missing resolution. If a real-number target is eventually written into integer .PRE, the value still becomes a whole number according to the conversion behavior used by the logic. Scaling the number before the write also fails because the timer interprets the resulting integer in milliseconds, not tenths of a millisecond.

Separate preset resolution from event accuracy

A 1 ms preset step does not mean the .DN transition reaches application logic with 1 ms accuracy. The timer instruction is evaluated when its task runs. Task period, scan variation, other scheduled work, and the instruction's position in the execution path affect when logic observes completion.

If task execution takes more than 1 ms, watch .ACC. It can advance by more than one millisecond between observations and can appear greater than .PRE. That is not a fractional-preset fault; it shows that the program did not evaluate the timer at every millisecond boundary.

A repeating timer adds another delay path. The application must observe .DN, perform the shift, clear or disable the timer, and enable the next interval. Those actions happen at task execution boundaries. The measured period can therefore exceed the nominal preset, and scan variation produces jitter around the event edges.

Choose the fix from the symptom

Pick the architecture from the physical tolerance, not from the number of decimal places displayed in an operator entry field.

Configure an average fractional interval

For an average-only requirement, distribute integer presets so their arithmetic mean equals the requested interval. For a target between 100 ms and 101 ms:

mean preset = (sum of integer presets) / number of cycles
fraction using 101 ms = target interval - 100 ms

For 100.2 ms, command 101 ms for one of every five cycles and 100 ms for the other four. The nominal preset total is 501 ms over five cycles, giving 501 / 5 = 100.2 ms.

For 100.9 ms, command 101 ms for nine of every ten cycles and 100 ms once. The nominal preset total is 1009 ms, giving 1009 / 10 = 100.9 ms. A claim of 101.9 ms for that pattern is an arithmetic error.

1. Store the requested interval separately from the timer's integer .PRE.
2. Split the request into its whole-millisecond value and fractional remainder.
3. Add the fractional remainder to a running error value once per requested interval.
4. Use the upper integer preset when that running value reaches one millisecond; subtract one millisecond from the running value. Otherwise, use the lower preset.
5. Update .PRE only at the boundary between intervals, before starting the next timing cycle.
6. Trigger BSL once from the completion event, then restart the timing sequence.

Spread the longer intervals through the sequence instead of grouping them when instantaneous phase error matters. The distribution changes short-term phase behavior but not the calculated mean.

This method controls only the mean programmed preset. Actual completion edges still include task and restart delays, so the observed average event period may be longer than the preset average.

Track machine position when time is the wrong variable

A shift register often models material moving down a line. Time-based shifting works only while speed remains sufficiently constant and slip, acceleration, stops, and restart behavior stay within the process tolerance.

Use position-based triggering when each bit represents a physical distance:

1. Identify a repeatable motion signal, such as conveyor sprocket teeth or an encoder on the moving mechanism.
2. Define one BSL event as a measured increment of travel rather than an elapsed interval.
3. Count motion events and generate one pulse when the configured travel increment is reached.
4. Pause naturally when motion stops because no position events arrive.
5. Compare register transitions with actual object locations across speed changes.

If the real requirement is object presence rather than calculated travel, detect the objects at the relevant points instead of extending a timing model. For tightly controlled motion or sub-millisecond event placement, use a dedicated module or motion controller designed for that timing domain.

Verify the interval at the event that matters

Do not validate the change by watching .PRE alone. Measure where the application consumes the timer completion.

1. Timestamp each one-shot event that triggers BSL. A GSV can access the internal 1 MHz WallClockTime for higher-resolution measurement.
2. Calculate consecutive event intervals, then record minimum, maximum, and mean values.
3. Compare the measured mean with the requested mean and compare the interval spread with the process tolerance.
4. Check cumulative phase error over the full operating period. A correct average should prevent unbounded drift caused by always rounding in the same direction.
5. Measure the physical result. Use the motion feedback, object sensor, or external timing instrument appropriate to the controlled event.

The 1 MHz clock improves timestamp resolution; it does not cause ladder logic to execute every microsecond. The task still detects and acts on events when scheduled. If an output edge or physical position has the tolerance, test that edge or position rather than treating an internal timestamp as final proof.

Avoid the fixes that waste time

• Writing a decimal directly to .PRE: The timer stores a double integer, so the fractional portion cannot remain.
• Replacing TON with RTO: Retention does not change the 1 ms timebase.
• Assuming 101 ms means a completion edge exactly 101 ms later: Task evaluation and restart logic affect when the application sees the edge.
• Alternating presets without measuring the output: The arithmetic mean can be right while individual intervals or physical positions remain outside tolerance.
• Driving BSL from a sustained condition: The register can shift on successive task executions instead of once per timer cycle.
• Tuning time to correct position drift: Conveyor slip or speed variation requires position or object feedback, not more decimal places.

FAQ