Configuring Hidden Bypass Signal in Siemens PCS 7 APL VlvL V9.0

Overview

The Siemens PCS 7 Advanced Process Library (APL) VlvL (Valve Logic) block is the standard type for motor-operated and solenoid valve control. Beginning with APL V9.0 the standard faceplate of a VlvL instance exposes three status indicators immediately to the left of the Permit/Interlock/Protect (PIP) button: a Bypass symbol, a Quality Code indicator, and a Padlock (lock/unlock) symbol. The Bypass symbol is the visible output of the AND-combination of two status bits on the VlvL block: Status1 bit 30 (Permit enabled) and Status3 bit 11 (Hidden bypass signal in Permit). Activating the symbol requires a correctly configured upstream Interlock-02 (Intlk02) block, the proper feature-bit settings on both blocks, valid bypass-license inputs, and a clean PCS 7 signal status of 16#00 on the connected inputs.

The same hidden-bypass naming convention exists across the PCS 7 family; the SIMOCODE pro PCS 7 Library V9.0 SP3 reserves a closely related set of bits in its motor-protection block, where the bit numbering convention differs from VlvL. The SIMOCODE pro manual lists Status3 bit 29 as Hidden bypass signal in Permit and Status3 bit 30 as Hidden bypass signal in Interlock Reverse — see the SIMOCODE pro PCS 7 Library V9.0 SP3 manual for the exact mapping. The VlvL numbering should be re-confirmed against the installed APL manual revision on the Siemens Industry Online Support portal.

Block Architecture: VlvL and Intlk02

The VlvL block implements a Permitted/Interlocked/Protected state machine. The Permit path is the interlock-aggregation result; the Interlock path is the protection path; the Protect path is the safety-critical trip path. In standard PCS 7 usage, the Permit input of VlvL is driven by the aggregated output of an Intlk02 block, which contains the bypass-evaluation logic and the operator-level bypass licenses that the hidden-bypass feature depends on.

Typical CFC topology:

• VlvL (e.g., VLV_001) — receives Permit from Intlk02.OUT, drives the valve command outputs.
• Intlk02 (e.g., INTLK_001) — aggregates two interlock sources (INO1, INO2) and exposes the hidden-bypass status used by VlvL.
• Upstream driver blocks (e.g., CH_AI, CH_DI, derived logic blocks) — provide the INO1 and INO2 Boolean values plus the PCS 7 signal-status attribute.

Feature Bits That Gate the Hidden Bypass

Two feature bits must be set for the hidden-bypass symbol to render and to track state changes in runtime:

If either bit is not set the Bypass symbol remains hidden regardless of upstream wiring. Both bits are persistent and survive CFC compile / download cycles; they are part of the block instance and are stored in the offline / online database of the S7 AS.

Status Word Bit Mapping

The Bypass symbol in the VlvL V9.0 faceplate is the AND-combination of the following two bits:

• Status1.bit 30 — Permit enabled. Indicates the Permit path is active and not revoked by a Protective trip. This is the master enable for the symbol.
• Status3.bit 11 — Hidden bypass signal in Permit. TRUE when Intlk02 reports that at least one connected signal (INO1 or INO2) is bypassed while the aggregated OUT still carries good quality (16#00).

BypLi01 and BypLi02 Configuration

Intlk02 exposes two bypass-license inputs that gate the operator's ability to bypass each connected signal path independently. The bypass license is the authorization to put a path into the bypassed state from the operator faceplate; it is not the bypass state itself.

With either BypLi set to 0 the operator cannot perform the bypass, and Intlk02 will not raise the hidden-bypass status to TRUE. The license is typically tied to a role-based authorization in the PCS 7 User Administration and may be driven by a process-condition tag (for example, maintenance mode active).

Signal Status 16#00 Requirement

INO1 and INO2 carry a PCS 7 signal-status attribute propagated from the upstream driver block. The signal status is encoded as a single-byte hexadecimal value in the low byte of the value attribute; the high byte carries the value itself. For the hidden-bypass symbol to indicate a clean bypassed, good quality state, both inputs must carry signal status 16#00 (good). Degraded statuses suppress the hidden-bypass evaluation and surface in the Quality Code indicator of the VlvL faceplate.

The signal status must be wired through every stage of the CFC chain. A common field error is to pass only the Boolean value from a derived logic block (e.g., a custom AND gate) without the status, which collapses the quality to 16#00 locally but masks any upstream degradation. The recommended practice is to use the APL composition blocks (And02, Or02) which propagate signal status correctly.

Step-by-Step CFC Configuration

1. Open the CFC chart that contains the VlvL block in the PCS 7 engineering station (SIMATIC Manager / PCS 7 V9.0).
2. Insert an Intlk02 block from the PCS 7 APL library onto the chart sheet.
3. Connect the upstream interlock sources to Intlk02.INO1 and Intlk02.INO2. Confirm that the signal-status attribute is wired through from the driver block (use the Signal Status column in the CFC interconnection view).
4. Connect Intlk02.OUT to VlvL.Permit.
5. Open the Object Properties of Intlk02 and set Feature.bit 2 = 1 in the I/Os tab.
6. Open the Object Properties of VlvL and set Feature2.bit 2 = 1 in the I/Os tab.
7. Configure BypLi01 = 1 and BypLi02 = 1 on Intlk02. These may be hard-wired constants or driven by a maintenance-mode tag.
8. Compile the chart and download the program to the AS (target system).
9. Open the VlvL faceplate in WinCC Runtime and confirm the Bypass and Quality Code indicators appear to the left of the PIP button.
10. From the operator's Bypass dialog, set INO1 (or INO2) to Bypassed and verify that Status3.bit 11 transitions to TRUE in online monitoring of Intlk02.

Online Monitoring Procedure

Use the CFC online view to confirm the hidden-bypass state end-to-end:

1. Right-click the Intlk02 block and select Monitor (or press the eye icon).
2. Open the VlvL block in the same way.
3. In the Intlk02 faceplate, set INO1 to Bypassed via the Bypass dialog (operator right & license required).
4. Observe the change in Intlk02.Status3.bit 11 — it should transition from 0 to 1.
5. Observe the change in VlvL.Status3.bit 11 — it should also transition from 0 to 1 because the bit is propagated through the Permit path.
6. Confirm that VlvL.Status1.bit 30 (Permit enabled) remains 1 during the bypass action. If it drops to 0, the Protect path has been triggered and the Bypass symbol will clear.
7. Confirm the faceplate Bypass symbol renders green and the Quality Code indicator stays at 16#00.

Verification Checklist

• Symbol visibility: In the standard view of the VlvL faceplate, confirm the Bypass padlock/symbol and Quality Code indicator render to the left of the PIP button.
• Bypass action: From the operator's Bypass dialog, set the corresponding INO1 or INO2 to Bypassed. In online monitoring, Status3.bit 11 (Hidden bypass signal in Permit) on Intlk02 should transition to TRUE.
• Quality Code: The Quality Code indicator should remain 16#00 (green) while both inputs are bypassed with good upstream quality. If quality degrades, the indicator turns yellow or red and the Bypass symbol hides.
• Status1.bit 30: Verify the Permit-enabled bit remains TRUE while the hidden bypass is active. If the Permit input is revoked (for example, by a Protective trip), Status1.bit 30 goes FALSE and the Bypass symbol clears.
• Round-trip release: Releasing the bypass from the operator dialog must drop Status3.bit 11 back to 0 within one PCS 7 scan cycle and re-evaluate the interlock chain.

Troubleshooting Matrix

Common Pitfalls

• Setting only one of the two feature bits — the symbol will not render at all.
• Forgetting to wire the signal-status attribute from the driver block to INO1 / INO2 — the hidden-bypass evaluation requires 16#00 to expose the symbol.
• Routing multiple interlock sources through a single INO without the appropriate PCS 7 OR/AND composition. Intlk02 expects two distinct connected signal paths.
• Confusing VlvL bit numbering with SIMOCODE pro block numbering. The SIMOCODE pro PCS 7 Library V9.0 SP3 reserves bit 29 for Hidden bypass signal in Permit and bit 30 for Hidden bypass signal in Interlock Reverse — see the SIMOCODE pro PCS 7 Library V9.0 SP3 manual. Always verify VlvL numbering against the installed APL manual revision.
• Assuming the bypass dialog is the same as the hidden-bypass symbol. The dialog drives the bypass state; the symbol is the visible summary. They are linked through Status3.bit 11 on Intlk02.
• Authorizing the bypass at the user level but not at the engineering level (BypLi = 0). The two are independent: a user with operator right can still be denied bypass at the CFC layer.

Migration and Version Notes

When upgrading an existing PCS 7 project from APL V8.x to V9.0, the new VlvL faceplate elements (Bypass, Quality Code, Padlock) are introduced without an automatic migration script. Engineering teams should:

1. Audit all VlvL instances for the presence of an upstream Intlk02 block. Where the Permit input is wired from a non-Intlk02 source, insert an Intlk02 instance and re-wire.
2. Apply Feature.bit 2 on Intlk02 and Feature2.bit 2 on VlvL globally using a CFC mass-operation if the engineering volume justifies it.
3. Recompile the OS server and transfer the runtime to pick up the new faceplate resources.
4. Validate each valve loop in the PCS 7 Maintenance Station by performing a controlled bypass / release cycle.

Edge Cases and Field Observations

• Permit tied to maintenance mode: BypLi01 / BypLi02 are often driven by a plant-wide maintenance mode tag. If maintenance mode is reset while a bypass is active, the bypass persists until the operator releases it; Status3.bit 11 remains TRUE but the BypLi input returns to 0, blocking further bypasses.
• AS cold restart: After an AS cold restart, the bypass state of Intlk02 resets to 0 and the hidden-bypass symbol clears. The operator must re-establish the bypass. This is by design and aligns with safety requirements.
• AS warm restart: After an AS warm restart, the bypass state is retained; the hidden-bypass symbol remains visible if upstream conditions are still met.
• Cross-AS simulation: When using PCS 7 S7-PLCSIM, the signal-status attribute may not propagate identically to physical I/O. Verify the hidden-bypass behavior on the real AS before commissioning.

FAQ