Configuring S7-1200 First Cycle Detection in TIA Portal

Overview

The Siemens S7-1200 programmable logic controller does not expose a discrete "Initialization flag" block comparable to the LOGO! logic relay toolbox, where a dedicated first-cycle marker sits in the constant/connector library. First-cycle detection on S7-1200 must be constructed from one of three native mechanisms: a dedicated startup Organization Block (OB100), the System Memory Byte (SMB) "First cycle" bit, or a user-defined edge-latched pattern that is portable across controller families.

This reference documents each approach with parameter-level detail, the TIA Portal configuration sequence, and a working three-state fan sequencer that demonstrates the practical difference between one-shot startup logic and a continuous first-cycle flag. The methods are valid for the entire S7-1200 CPU range (CPU 1211C / 1212C / 1214C / 1215C / 1217C) running firmware V4.2 or later, with engineering in TIA Portal V16 SP1 through V18.

Prerequisites

Authoritative reference: S7-1200 Programmable Controller System Manual (Siemens Support).

Method Selection Matrix

Method 1 — OB100 Startup Organization Block

OB100 is the S7-1200 startup Organization Block. It executes exactly once on every STOP → RUN transition, before OB1 begins cycling. This makes it the cleanest location for one-time initialization of variables, force-resetting of sequencer counters, or pre-loading of shift registers. Because OB100 runs before OB1, any tag assigned there is guaranteed to be at its initial value when the first OB1 scan begins.

Execution Sequence on STOP → RUN

1. CPU firmware clears all non-retentive memory (M, DB non-retain, outputs).
2. Firmware restores retentive memory (DB-retain, M-retain) from backed-up storage.
3. Firmware calls OB100 once.
4. OB100 completion triggers OB1 cyclic execution; OB1 continues until next STOP or power loss.

If OB100 is missing from the project, the CPU performs default startup behavior without executing user initialization code. Adding OB100 does not change the cold-restart sequence — it inserts a one-shot execution slot the user can program.

Creating OB100 in TIA Portal

1. Open the S7-1200 device in the project tree.
2. Expand “Program blocks”.
3. Double-click “Add new block”.
4. Select “Organization block” from the type list.
5. Choose OB number 100 from the dropdown. TIA Portal auto-fills the symbolic name “Startup”.
6. Confirm the programming language (LAD / FBD / ST) and click OK. The OB100 editor opens.

Initialization Code Pattern

Place initialization logic directly in OB100. Example using Structured Text:

Equivalent LAD implementation places a Move block on the left power rail moving the constants 0 and FALSE into the corresponding tags. No enable condition is required — the entire OB100 body runs exactly once.

OB100 Start Information

OB100 exposes a temporary local tag interface populated by the firmware with start information. In TIA Portal the interface can be inspected via “Properties → Interfaces”. The relevant BOOL inputs are:

Branching on Remanence_State allows different initialization paths for cold restart (full reset) versus warm restart (preserve process state and only re-initialize transient flags). Most field deployments use the unconditional initialization pattern above; the start info is reserved for applications where preserving a sequence position across a brief power dip is critical.

Limitations of OB100

• OB100 executes only on STOP → RUN. A subsequent STOP → RUN via the mode switch re-triggers initialization; a CPU power cycle behaves identically.
• If OB100 contains a programming error that drives the CPU to STOP, the diagnostic buffer records an OB100 startup error and OB1 does not execute. The system fault LED activates.
• Execution time of OB100 counts against the configured maximum cycle time monitoring. Keep initialization code small (sub-millisecond).
• OB100 cannot be called manually from OB1 — it is firmware-invoked only.

Method 2 — System Memory Byte First Cycle Bit

The S7-1200 System Memory Byte provides standardized status and clock bits the firmware updates every OB1 scan. Bit 0 of the enabled System Memory Byte is the “First cycle” flag: set TRUE for the first execution of OB1 after a STOP → RUN transition and cleared FALSE on all subsequent OB1 cycles until the next STOP → RUN.

System Memory Byte Bit Assignments

Per the S7-1200 System Manual, when a System Memory Byte is enabled the firmware assigns the following semantics to the eight bits:

Enabling the System Memory Byte

1. In the project tree, select the S7-1200 CPU device (not a program block).
2. Open “Properties” → “System and clock memory”.
3. Check “Enable system memory byte”.
4. Set the address (default %MB0). This address must not collide with any tag already in use elsewhere in the program.
5. Optionally enable “Enable clock memory byte” and set its address (default %MB1).
6. Click “OK” and download the hardware configuration to the CPU.

Using the First Cycle Bit

Once enabled, the first-cycle bit is addressable as %M0.0 (assuming the default address %MB0). Use it in OB1 to perform first-scan logic that must execute within the main cyclic program:

The advantage over OB100 is that the same logic is accessible from any FB/FC without requiring that block to be called from OB100. The disadvantage is that the first-scan window is exactly one OB1 cycle, so very long cycle times can cause races if the consuming logic runs in a slower OB (e.g., OB35 cyclic interrupt).

Timing Diagram of First-Cycle Pulse

STOP         RUN
  |           |
  v           v
  +-----------+-----------------> Time
      |       |
      | OB100 | OB1 #1   OB1 #2   OB1 #3 ...
      | runs  |
      |       v          v         v
%M0.0        ___________                            
            |          |___________________________ 
            |  TRUE    | FALSE   FALSE   FALSE
            +----------+--------+--------+--------+
            ^ First cycle pulse

Method 3 — Latched First-Cycle Edge Pattern

A platform-portable alternative is to construct the first-cycle flag manually. The pattern uses edge-detection latching identical in S7-1200, S7-1500, S7-300/400, and Allen-Bradley CompactLogix:

Where DB_Retain.bInitialized is a BOOL declared as RETAIN (retentive). After the first execution, the latch stays TRUE across all subsequent OB1 cycles. On STOP → RUN, the latch is preserved (because it is retentive) — meaning this pattern only initializes on the very first CPU startup or after a memory reset (MRES) that clears retentive data. This behavior differs from Methods 1 and 2, which re-initialize on every STOP → RUN.

For non-retentive latching where STOP → RUN should re-initialize, declare the latch in M-memory or a non-retentive DB:

Edge-Detection Variants with R_TRIG / F_TRIG

For applications where the first-cycle signal must trigger multiple FBs in parallel, use an R_TRIG (rising-edge detection) on a one-shot pulse derived from SMB bit 0:

Implementation: Three-State Fan Sequencer

The reference application is a fan sequencer driven by a single push button:

• First impulse: FAN1 ON
• Second impulse: FAN2 ON (FAN1 retained or released per process spec)
• Third impulse: Both OFF, sequence resets

Two implementations follow — a counter/modulo pattern and a shift-register pattern — each initialized on first cycle via the SMB method.

Data Block Definition (DB_Sequencer)

Sequencer Logic — Counter Variant (Structured Text)

Counter Variant State Table

Sequencer Logic — Shift Register Variant (Structured Text)

Shift Register Variant State Table

First-Cycle Initialization for the Sequencer

Add this network to OB1 (Method 2) to force the sequencer into a known state on every STOP → RUN:

Step-by-Step TIA Portal Configuration

1. Open or create a TIA Portal project targeting your S7-1200 CPU.
2. Add a new device: “Controllers → SIMATIC S7-1200 → CPU → [your model]”.
3. Configure the CPU IP address and PROFINET device name if applicable.
4. Open the CPU device view and navigate to “Properties → System and clock memory”.
5. Enable “System memory byte” and set address %MB0 (default).
6. In the project tree, add a new Data Block “DB_Sequencer” with the tags listed above. Set all sequencer tags as non-retentive.
7. Open OB1 and write the three networks shown in the sequencer logic section above, preceded by the first-cycle reset network.
8. Save and compile the project (right-click the CPU → “Compile → All”).
9. Download the hardware and software to the CPU. The CPU will STOP then RUN automatically.
10. Open an online watch table on DB_Sequencer and %MB0 to observe the first-cycle pulse.

Verification and Commissioning

After download, verify each method independently before integrating the sequencer:

1. Method 1 verification: Place a breakpoint or single-step in OB100. Trigger a STOP → RUN transition via the mode switch or TIA Portal “STOP → RUN” button. Confirm OB100 executes exactly once and the monitored tags reach their initial values.
2. Method 2 verification: In an online watch table, force %MB0 to display. Toggle the CPU from RUN → STOP → RUN. Observe %M0.0 rising to TRUE for exactly one OB1 scan, then falling to FALSE on the next scan.
3. Method 3 verification: With “DB_Retain”.bInitialized declared RETAIN, perform a STOP → RUN. Confirm initialization does NOT repeat. To re-test, perform a memory reset (MRES) to clear retentive data.
4. Sequencer verification: Manually pulse %I0.0 three times. Confirm the FAN1 / FAN2 outputs follow the expected state table. Repeat from cold STOP → RUN to confirm first-cycle reset behavior.
5. Watch table sample: Add tags %M0.0, DB_Sequencer.iImpulseCount, DB_Sequencer.bFan1, DB_Sequencer.bFan2, and %I0.0 to a single watch table for live monitoring during commissioning.

Watch Table Layout for Live Commissioning

Troubleshooting Matrix

Safety and Process Considerations

First-cycle logic frequently sets outputs to a safe state. For fan control, ensure:

• Outputs driving contactors pass through hardwired E-stop circuitry rated to interrupt motor locked-rotor current.
• The first-cycle reset does not energize fans unless the process explicitly requires it; default to OFF.
• If using RETAIN to preserve sequence position across power dips, validate that the mechanical state of the fans matches the retained counter before relying on it.
• For safety-rated applications (SIL 1 / SIL 2 per IEC 61508), first-cycle logic must not be the sole means of de-energizing the load. Use a safety relay or F-CPU safety function.

Cross-Platform Notes

The three methods translate as follows on related Siemens platforms:

FAQ