Configuring S7-1200 HSC Frequency Mode for HTL Encoder RPM

Overview: Counting vs. Frequency Measurement with HTL Encoders on S7-1200

When a Siemens S7-1200 (specifically a 1215C DC/DC/DC, part number 6ES7215-1AG40-0XB0) is wired to an HTL incremental encoder, two distinct behaviours are often observed depending on how the High-Speed Counter (HSC) is configured:

• Count mode: The HSC accumulates every rising (or rising+falling, in quadrature) edge. The value persists in the process image even after rotation stops. It never resets to zero unless the program calls CTRL_HSC with a software reset or the hardware is re-initialised.
• Frequency mode: The HSC measures input pulses per unit time internally and reports a rate (Hz). When rotation stops, the reported rate collapses to 0 because no new pulses are arriving within the integration window.

If your requirement is RPM that goes to zero automatically when the shaft stops, you must select Frequency as the operating mode in the HSC device configuration. Selecting Count mode and then asking "why doesn't it reset to 0?" is a configuration mismatch, not a fault.

S7-1215C HSC Hardware Capabilities

The S7-1215C DC/DC/DC provides six onboard high-speed counters. Each counter is mapped to dedicated digital inputs on the CPU:

Firmware v4.6 (the latest validated release at time of writing) preserves the HSC frequency ceiling at 100 kHz for the DC/DC/DC variants. Relay-output CPUs are limited to 30 kHz on the relevant HSC inputs. Confirm your CPU variant against the article number before specifying an encoder with ppr that would exceed the limit.

Source: S7-1200 Programmable Controller System Manual.

HTL Encoder Signal Levels and Wiring

HTL (High-Threshold Logic) encoders output signals swinging between 0 V and typically 10–30 V DC, whereas TTL encoders swing between 0 V and 5 V DC. Common HTL devices used in this application class include:

• Pepperl+Fuchs 10-11651_R-1200: 1200 ppr, push-pull HTL output
• Pepperl+Fuchs 10-15631_R-1024: 1024 ppr, push-pull HTL output (shown as the encoder in the referenced demo)
• Beckhoff 05.2420.1230.1024.5009: 1024 ppr, HTL output

Push-pull HTL outputs are driver-side powered by the encoder's 24 V supply, so they do not require external pull-up resistors on the S7-1200 inputs (unlike open-collector NPN outputs). The S7-1200 1215C DC/DC/DC inputs are type 1 / type 3 per IEC 61131-2 and accept 24 V signals directly.

Wiring checklist:

1. Connect encoder power (24 V DC) to a clean, regulated supply. Encoder supply and PLC input supply should share the same reference ground.
2. Route encoder phase A to the HSC's "A / pulse" input. On HSC1 of the 1215C, this is I0.0.
3. If using quadrature (x2 or x4 resolution), wire phase B to "B / direction" (I0.1 for HSC1).
4. Tie encoder cable shield to earth ground at one end only, typically at the panel entry, to break ground loops.
5. Keep encoder cable segregated from VFD output cables by at least 200 mm to avoid capacitive noise injection.

Digital Input Filter Configuration

The most common reason an HSC "counts correctly at low speed but loses pulses at high speed" is the default digital input filter. On the S7-1200, each input has a configurable input filter in the device configuration under Properties → Digital Inputs → Channel [n] → Input Filter. The valid range is 0.1 µs to 20 ms.

The default filter is approximately 6.4 ms — appropriate for pushbuttons, but catastrophic for a 100 kHz encoder. At a 1200 ppr quadrature (x4) encoder rotating at 3000 rpm, the pulse rate is:

f = (1200 × 4 × 3000) / 60 = 240 kHz

That signal is well above the 100 kHz ceiling of the 1215C HSC, but if you select single-phase counting at 1000 rpm:

f = (1200 × 1 × 1000) / 60 = 20 kHz

Even at 20 kHz, a 6.4 ms filter blocks every single pulse. Configure both phase A and phase B inputs (and any synchronisation input, if used) to the minimum filter:

1. Open the CPU device configuration in TIA Portal V17 or later.
2. Select Properties → Digital Inputs.
3. For each HSC input channel (e.g. %I0.0 and %I0.1), set the Input Filter value to 0.1 µs.
4. Compile and download the hardware configuration to the CPU. Filter changes do not apply until the new hardware configuration is downloaded.

HSC Operating Modes: Count, Frequency, Period

The HSC supports three measurement modes selectable per channel under Properties → High-Speed Counter (HSC) → Operating mode:

For RPM measurement the user expects, Frequency mode is the correct choice because:

• It returns a rate (events per second), which maps directly to RPM by multiplication.
• The integration window smooths jitter in quadrature decoding.
• When pulses stop arriving, the HSC reports 0 Hz automatically — no software reset logic required.

Period mode is preferred when the encoder spins slowly enough that frequency mode returns too few pulses per integration window for stable readings. Below roughly 1 Hz output the period mode delivers finer resolution.

RPM Calculation Formula

The published RPM formula for frequency-driven HSCs is:

RPM = (f_Hz × 60) / PPR_effective

where PPR_effective = PPR × counting_mode_factor.

For the counting modes available on the 1215C HSC, the factor is:

Worked example with the referenced Pepperl+Fuchs 10-15631_R-1024 (1024 ppr) and 4x quadrature:

PPR_effective = 1024 × 4 = 4096

For a measured frequency of 20 480 Hz:

RPM = (20 480 × 60) / 4096 = 300 RPM

The alternative formula written as RPM = (PPR / f_Hz) × 60 is inverted; verify the form before copying. In TIA Portal the HSC directly outputs frequency, so the multiplier pattern above is the only correct one.

Step-by-Step TIA Portal Configuration

1. Add the CPU 1215C DC/DC/DC (6ES7215-1AG40-0XB0) to the project. Verify firmware version is v4.6 or later.
2. Open Device Configuration → Properties → High-Speed Counter (HSC1).
3. Enable HSC1 and assign input I0.0 (phase A) and I0.1 (phase B) if using quadrature.
4. Select Two-phase as the counter type and 4x as the evaluation.
5. Under Operating mode, select Frequency.
6. Set the integration window to 100 ms (default) for general-purpose RPM. Increase to 1000 ms for better low-speed stability; decrease to 10 ms for fast response.
7. Set Initial counter value = 0 and Initial reference value = 0.
8. Switch to Properties → Digital Inputs and set the input filter on %I0.0 and %I0.1 to 0.1 µs.
9. Compile the project (Project → Compile → Software (rebuild all)) and download both the software and the hardware configuration to the CPU.
10. Add a watch table or HMI tag to read the HSC frequency value. The default symbolic name is "HSC1_Frequency" in the HSC DB.

CTRL_HSC Instruction for Software Reset

If a Count-mode application legitimately requires a counter reset (e.g. homed-position applications), use the CTRL_HSC instruction from Instructions → Counting / Measurement → High-Speed Counter:

// SCL example
"HSC1_DB".CTRL_HSC.HSC := 1;           // HSC channel
"HSC1_DB".CTRL_HSC.DIR := false;        // count direction irrelevant for reset
"HSC1_DB".CTRL_HSC.CV := 0;             // new current value
"HSC1_DB".CTRL_HSC.RV := 0;             // reference value
"HSC1_DB".CTRL_HSC.PERIOD := true;      // period measurement on/off
"HSC1_DB".CTRL_HSC.NEW_CV := true;      // accept CV on next cycle
"HSC1_DB".CTRL_HSC.CTRL := true;        // enable control

IF "HSC1_DB".CTRL_HSC.DONE THEN
    "HSC1_DB".CTRL_HSC.CTRL := false;   // pulse-style execution
END_IF;

Calling CTRL_HSC with CV = 0 and NEW_CV = TRUE writes the new counter value on the next HSC update cycle. In Frequency mode, this instruction is not required because the HSC returns 0 Hz automatically when pulses stop.

Verification Procedure

1. Force the encoder to a known RPM using a reference (calibrated stroboscope, second encoder on the same shaft, or motor controller read-out).
2. Monitor the HSC frequency tag with a watch table. Confirm the reading is stable to within ±1% of the reference RPM × PPR/60.
3. Stop the shaft. Confirm the HSC frequency drops to 0 within one integration window.
4. Restart the shaft. Confirm the HSC resumes reporting frequency within the next integration window.
5. Run the system at maximum specified RPM for 10 minutes and verify the value does not drift, indicating no lost pulses.

Troubleshooting Matrix

Comparison: Frequency vs Period vs Count for RPM

Encoder Selection Notes

Pick PPR such that PPR_effective × RPM_max / 60 < HSC_max (100 kHz for 1215C DC/DC/DC). For 10 000 RPM max with 4x quadrature on a 1200 ppr encoder:

1200 × 4 × 10 000 / 60 = 800 kHz → exceeds limit

In this case reduce PPR to 200 or 250, or switch to 1x evaluation, or use a frequency divider on the encoder side. Always leave at least 20% headroom below the 100 kHz ceiling to account for edge jitter and CPU scan-to-scan latency.

Safety and Diagnostic Considerations

• Use the HSC's hardware interrupt on a configurable reference value (CV = RV) to detect a stuck or runaway counter. This generates a process interrupt and can be wired to a stop category per IEC 60204-1 if the encoder is in a safety-relevant loop.
• Monitor the HSC status word for STS_SW_GATE (software gate state) and STS_C_DN / STS_C_UP for direction state, exposed automatically in the HSC instance DB.
• If the encoder is part of a safety-rated speed monitor (SIL 2/3 per IEC 61508), the S7-1200 onboard HSC is not safety-rated. Route safety-related speed sensing to a certified safety relay or a fail-safe encoder interface.