Configuring VIPA CPU 316 as DP Slave on S7-300 PROFIBUS Master

Overview: VIPA CPU 316 as Intelligent DP Slave on a Siemens S7-300 Master

Integrating a VIPA CPU 316 into a Siemens SIMATIC S7-300 PROFIBUS DP network as an intelligent DP slave (I-slave) is a common requirement when migrating a VIPA-based subsystem into a Siemens master. The most frequent commissioning failure is the immediate appearance of SF (group fault) on the master and a flashing BF (bus fault) LED on the CPU 314C-2DP, with the diagnostic buffer reporting "DP slave differs from configuration" even though the I/O addresses and slot layout appear correct.

This article documents the exact root cause (incorrect slave device type / missing VIPA GSD), the correct configuration path in STEP 7 V5.x and TIA Portal, the master-slave assignment procedure using the official Siemens DP-slave-to-master assignment procedure, and the data-consistency workaround required because the VIPA CPU 316 firmware does not support the "Data consistency over the full length" mode that SFC14 / SFC15 require.

Problem Description and Diagnostic Signature

Reference configuration:

When the master is downloaded with the slave configured as any Siemens DP device (typically a CPU 315-2DP V1.2 used as a placeholder), the CPU 314C-2DP raises:

• SF LED – solid ON (group fault, diagnostic buffer entry present).
• BF LED – flashing at 2 Hz (PROFIBUS bus fault, slave not responding or wrong type).
• Diagnostic buffer entry: "DP slave diagnostics: station failure" followed by "DP slave differs from configuration" on the next startup attempt.
• Module Information in STEP 7 → DP Slave Diagnostics tab shows a red entry for the slave with "Slave does not exist / wrong module type".

Root Cause Analysis

Two independent defects combine to produce the SF/BF signature:

1. Wrong device type in the STEP 7 hardware catalog. The VIPA CPU 316 is not a Siemens product. STEP 7 cannot identify it unless the matching VIPA GSD file is installed and the slave is inserted from the GSD-derived catalog folder. A "same I/O area" argument is irrelevant: the master's start-up routine validates the device identity, not the address mapping.
2. Asymmetric configuration of the VIPA CPU 316 itself. The VIPA CPU 316 must be configured in its own STEP 7 project (or in the same project) as a CPU 315-2DP slave with PROFIBUS interface set to DP slave and the same slot layout that will be exposed to the Siemens master. VIPA's documentation requires the local PROFIBUS network of the VIPA CPU 316 to use the VIPA GSD-derived profile on both sides of the link.

A third, separate limitation is the data-consistency behaviour documented in the VIPA manual: "Data consistency can only be guaranteed for one unit! The choice 'Data consistency by length' is not supported." This restricts use of SFC14 (DPRD_DAT) and SFC15 (DPWR_DAT) and forces a per-word/per-byte access pattern using direct I/O areas (PIW / PQW).

Prerequisites

• STEP 7 V5.5 + SP2 or later (V5.7 recommended), or TIA Portal V13/V14/V15/V16 with HSP for VIPA devices installed.
• VIPA GSD file for the CPU 316, downloaded from the official VIPA GSD file repository. Confirm the file name matches the CPU variant (e.g. VIPA_316-2DP12.GSD).
• CPU 314C-2DP with firmware V2.x or V3.x. Verify with PLC → Module Information → Diagnostic Buffer or the imprint on the MMC slot.
• VIPA CPU 316 with firmware SPEED7 V3.x or V4.x and an MPI/PROFIBUS programming cable.
• PROFIBUS DP cable with 9-pin D-sub connectors, terminated at both ends with 220 Ω between pins 3-8 and a 390 Ω pull-up / pull-down pair (standard PROFIBUS termination, switched on at the connector or the last device).
• STEP 7 project containing both masters' and slave's station, or two separate projects networked via the GSD file.

Step 1 – Install the VIPA GSD File

1. Download the GSD archive from VIPA and unpack it locally.
2. In STEP 7 V5.x: Options → Install GSD File… Browse to the unpacked *.GSD file and confirm.
3. Close and re-open HW Config so the catalog refreshes. The VIPA device appears under PROFIBUS DP → Additional Field Devices → I/O → VIPA (exact path depends on the GSD revision).
4. For TIA Portal: Options → Manage device description files (GSD), import the file, and update the device catalog.

Step 2 – Configure the VIPA CPU 316 as a DP Slave in its Own Project

1. Open the VIPA CPU 316 station in HW Config.
2. Insert the CPU 315-2DP (VIPA variant) into slot 2. The VIPA GSD maps the SPEED7 CPU 316 to a CPU 315-2DP V1.x type so that STEP 7 can edit it.
3. On the DP interface (X2), select DP Slave mode.
4. Switch to the DP slave properties tab and define the slots that will be visible to the Siemens master. Typical configuration: one 16-byte consistent slot for inputs and one 16-byte slot for outputs, mapped to virtual I/O areas inside the VIPA CPU.
5. Compile and download the VIPA project. The VIPA CPU 316 will power up reporting the configured slot layout on PROFIBUS.

Step 3 – Assign the VIPA Slave to the Siemens Master

Open the S7-300 master station (CPU 314C-2DP) in HW Config. Follow the procedure in Assigning the DP slave to a DP master:

1. Drag the VIPA CPU 316 (from the GSD catalog) onto the DP master system line at PROFIBUS address 3.
2. On the slave, click the Not assigned link and select the CPU 314C-2DP master from the Select DP master dialog. This is the assignment step that links the slave to the master without yet committing the slot layout.
3. Open the slave's Configuration tab and insert the same slot layout that the VIPA CPU 316 was programmed to publish (matching byte/word length and consistency). Mismatches here re-trigger "DP slave differs from configuration".
4. For TIA Portal / S7-1500 interop, see also Adding an I-slave to a DP master system (S7-300, S7-400, S7-1500).

Step 4 – Slot Alignment Between Master and Slave

The slot layout must be byte-exact. A typical 8-byte bidirectional configuration:

If the consistency column is set to Total length in the master but the VIPA CPU 316 firmware only supports Unit, the parameterisation handshake will fail and the master will log "DP slave parameterisation error" in the diagnostic buffer.

Step 5 – Data Transfer: SFC14/SFC15 Limitation and Workaround

SFC14 (DPRD_DAT) and SFC15 (DPWR_DAT) read and write consistent DP data areas. Internally, the CPU copies a contiguous data block in a single bus cycle, which requires the slave to support the same consistency model. The VIPA CPU 316 only supports unit consistency (1 word = 2 bytes), so calling SFC14/SFC15 will return error code W#16#8090 ("Address of the data area not configured in the process image of the DP slave") or, in some firmware revisions, the call completes but with corrupted data after the first byte.

Use direct process-image I/O access instead. The S7-300 master updates the I/O every bus cycle, so unit-consistent reads are safe for a single word:

ST example – 8-word input block from VIPA CPU 316 to DB100 of master:

// OB1 – read 8 words from slave inputs to DB100.DBX0
LAR1  P#DBX 0.0
LAR2  P#E 0.0
L     8
NEXT: L     EW [AR2,P#0.0]
      T     DBW [AR1,P#0.0]
      +AR2  P#2.0
      +AR1  P#2.0
      LOOP  NEXT

ST example – 8-word output block from DB200 of master to VIPA CPU 316 outputs:

// OB1 – write 8 words from DB200.DBB0 to slave outputs
LAR1  P#DBX 0.0
LAR2  P#A 0.0
L     8
NEXT: L     DBW [AR1,P#0.0]
      T     AW [AR2,P#0.0]
      +AR1  P#2.0
      +AR2  P#2.0
      LOOP  NEXT

For structures larger than 4 words, place the SFC14/SFC15 call inside a SER/DES (Send/Receive) block is not applicable. Instead, implement a handshake: read a control word, copy data on a rising edge, and write a status word. This avoids torn reads when the master cycle and the slave cycle are not phase-locked.

Step 6 – Diagnostics: Reading SF/BF After Configuration

After download, cycle power on both stations. The expected LED state is:

If the BF LED still flashes, perform a live diagnostic readback:

1. In STEP 7: PLC → Module Information → Diagnostic Buffer. The most recent entries are the parameterisation cycle and the configuration check. Decode the error code:

2. Use DP Slave Diagnostics tab → read Station status 1/2/3 bytes. 0x1C in Station status 1 indicates the slave is in wait for parameterisation; 0x44 means wait for configuration; 0xFF means ready for data exchange.

Verification Procedure

1. Force a known value into the VIPA slave's PIB 0..7 and observe the master PIW 0..7 in a VAT table. Both must show the same value, updated every DP cycle (typically 1-6 ms for 1.5 Mbps).
2. Toggle a bit in the master's PQW 0 and verify it appears in the VIPA's PAB 0 within one bus cycle.
3. Disconnect the PROFIBUS connector on the slave. The master SF LED must light within 2 s and the diagnostic buffer must show 0x13A2 station failure. Reconnect and confirm the error clears after the next parameterisation cycle.
4. Cycle power on the master only. The slave must re-enter data exchange automatically without manual intervention (auto-reconnect on master restart).

Troubleshooting Matrix

Performance and Timing Notes

At 1.5 Mbps (default STEP 7 DP bus profile) and a typical 8-byte input + 8-byte output configuration, the cycle time on a CPU 314C-2DP with one I-slave is approximately 1.0 ms. Increasing the slot length to 32 bytes raises the cycle to ~1.6 ms. The VIPA CPU 316 supports baud rates up to 12 Mbps; operation above 1.5 Mbps requires shielded PROFIBUS cable and a maximum segment length of 100 m (1.5 Mbps), 200 m (500 kbps), or 1.2 km (9.6 kbps). Do not mix repeaters from different vendors on the same segment when targeting 12 Mbps.

Common Pitfalls

• Configuring the VIPA CPU 316 as a Siemens CPU 315-2DP V1.2 in the Siemens master project. This compiles and downloads, but fails at run-up because the device identity check fails.
• Forgetting to install the GSD before inserting the slave. STEP 7 will offer to insert a placeholder Siemens device, which compiles but will not communicate.
• Mixing Unit consistency on one side and Total length on the other. The slave with the lower capability is the binding constraint.
• Using SFC14/SFC15 on multi-word structures where the slave cannot guarantee length consistency. The CPU will return W#16#8090 (address not in process image) or silently corrupt data after the first 2 bytes.
• Re-inserting a different GSD revision without rebuilding the master slot table. The internal slot index changes between firmware generations.

FAQ