Converting S7-200 SM0.0 SM0.1 SM0.5 to S7-1200 System Memory

Overview

Siemens S7-200 and S7-1200 use fundamentally different memory architectures for special status bits. S7-200 STEP 7-Micro/WIN programs rely on SM (Special Memory) bytes for always-on flags, first-scan bits, fixed-frequency clocks, and run-mode status. The most commonly used symbols are SM0.0 (Always On), SM0.1 (First Scan On), and SM0.5 (1 Hz clock). When porting an S7-200 program to a S7-1200 controller using TIA Portal, these SM references are not auto-translated; the converter leaves the tags as unresolved symbolic names with no address, generating "tag address not found" or "no assigned value" warnings during compilation.

The S7-1200 CPU exposes equivalent functionality through two configurable byte regions: the System Memory Byte and the Clock Memory Byte. Both are enabled under Device Configuration → CPU Properties → System and Clock Memory. Once enabled, the engineer assigns a free M-byte (for example, MB1 for system bits, MB20 for clock bits) and rewrites the SM symbol addresses in the program to the corresponding M-bit. This guide documents the exact mapping, the period/frequency math, the procedure, and the field-tested pitfalls observed during S7-200 → S7-1200 porting. Reference the official Siemens FAQ 41306542 for system and clock memory parameter details.

Prerequisites

• Source CPU: Siemens S7-200 (any CPU 21x or 22x family) with STEP 7-Micro/WIN project (.mwp).
• Target CPU: Siemens S7-1200 (CPU 12xx / 15xx family) supporting TIA Portal V13 SP1 minimum; V15, V16, V17, V18, or V19 recommended.
• Firmware baseline: Target S7-1200 CPU firmware ≥ V4.0 (System and Clock Memory configuration path is identical from this baseline).
• Project migration: TIA Portal "Migrate project" wizard to convert the .mwp to a .ap13 / .ap14 / .ap15 / .ap16 / .ap17 / .ap18 project, or manual port if migration fails.
• Hardware configuration: S7-1200 station with the CPU fully configured (signal modules, PROFINET, etc.) before system memory is enabled.
• Free M-byte ranges: At least 1 byte free for system memory and 1 byte free for clock memory. Confirm bytes do not overlap any data block, instance DB, or local stack.
• Symbol table access: PLC tags or symbol table editable to rename and re-address the SM symbols.

S7-200 Special Memory (SM) Reference

The S7-200 SM byte SMB0 is read-only and contains status bits that are refreshed by the operating system on every scan. The most relevant bits for ladder-logic initialization, edge detection, and periodic triggers are listed below.

The S7-200 SMB1 byte (status) is also commonly polled (SM1.0 zero flag, SM1.1 overflow, SM1.2 negative result, SM1.3 divide-by-zero) but is generally not required when migrating to S7-1200 because the new arithmetic operations set the CPU status word flags accessible via ST/LAD directly.

S7-1200 System Memory Bit Architecture

The S7-1200 System Memory Byte (also called "SMB" or "System Memory") is configured in the CPU properties. Unlike S7-200, where the SM byte is a fixed memory area at SMB0, the S7-1200 lets the engineer select any free M-byte. The default in TIA Portal is MB1; Siemens strongly recommends keeping MB1 unless there is an address conflict.

After enabling the System Memory Byte and selecting a byte address (e.g., MB1), the CPU operating system automatically maintains the following bit semantics on every scan:

S7-1200 Clock Memory Bit Architecture

The Clock Memory Byte provides 8 independent square-wave generators with binary-related frequencies. Unlike the system memory byte (where each bit has a fixed semantic), the clock memory byte produces a bit pattern where each bit toggles at half the frequency of the previous bit. The exact frequency depends on the bit position. The relationship between frequency f and period T in seconds is:

T = 1 / f

f = 1 / T

Using the canonical 1 Hz reference base, the bit pattern in the configured clock memory byte (e.g., MB20) is:

For the recommended selection of MB20 with the 1 Hz reference base, the bit positions produce these common signals:

The TIA Portal clock memory base is fixed at project download time; there is no runtime API to change it from user logic. To use a different base, edit the CPU properties, recompile, and re-download the project.

Conversion Mapping Table

The complete S7-200 → S7-1200 mapping using the recommended MB1 (system) and MB20 (clock) defaults is summarized below.

Step-by-Step Conversion Procedure

1. Open the migrated project in TIA Portal. Select the S7-1200 CPU in the project tree and double-click Device configuration.
2. Navigate to System and Clock Memory. In the inspector window, click Properties → System and Clock Memory.
3. Enable System Memory bits. Check the box Enable system memory bits and accept the default byte MB1, or change to a free byte such as MB100 if MB1 conflicts with local FB/FC stack usage.
4. Enable Clock Memory bits. Check the box Enable clock memory bits. Enter the byte address (MB20 is the convention; verify it does not overlap any data block).
5. Compile the hardware configuration. Press Ctrl+B or click the compile icon. Confirm zero errors.
6. Update the PLC tag table. Open PLC tags → Show all tags. Locate each unresolved SM symbol (e.g., SM0_0, SM0_1, SM0_5). For every tag:
   • Keep the symbolic name to avoid losing cross-references in the program.
   • Change the data type if necessary (Bool for SM bits).
   • Assign the new address. Example: SM0_0 → %M1.2, SM0_1 → %M1.0, SM0_5 → %M20.1.
7. Re-compile the program. All previously unresolved SM references must now resolve. If any "Address not assigned" or "Tag not found" errors remain, repeat step 6 for the affected tags.
8. Cross-check usage. Use Cross-references (Ctrl+Shift+F) to ensure every program block referencing the SM symbol uses the new M-address.
9. Download to CPU. Perform a full download (not just delta) the first time to ensure the system/clock memory configuration takes effect.
10. Verify online. Switch to online view; open the tag table for monitoring. Confirm M1.2 = 1, M1.0 pulses high on first cycle, M20.1 toggles at the expected period.

Symbol Naming Convention Recommendation

Renaming SM0_0 to SM0_0 while changing the address to %M1.2 preserves the program source line numbers and the symbol table history. Engineers porting a large codebase should adopt the following naming pattern:

Tag name        Address     Comment
SM0_0           %M1.2       "Always ON (mapped from S7-200 SM0.0)"
SM0_1           %M1.0       "First scan ON (mapped from S7-200 SM0.1)"
SM0_5           %M20.1      "1 Hz clock (mapped from S7-200 SM0.5)"
SM0_4           %M20.7      "60 s clock approximate; verify period for application"

This convention retains the original S7-200 symbol names, so any future review of the migrated program can immediately trace each reference back to its origin. It also avoids the multi-day task of renaming across hundreds of network references.

Clock Memory Period Calculations

When the S7-200 source used SM0.4 (60-second clock) or SM0.5 (1-second clock), the engineer must recalculate any process timing that depended on a fixed duty-cycle square wave. The relevant formulas are:

f = 1 / T   (frequency in Hz, period in seconds)

T = 1 / f   (period in seconds)

For the S7-1200 clock memory byte at MB20 (1 Hz base), the equivalent edges per minute for each bit are:

If the application requires an exact 60-second clock (S7-200 SM0.4 equivalent), the recommended approach is to use an IEC timer in a cyclic OB:

// SCL example: 60 s clock pulse on M200.0
"Clock_60s_IE" := FALSE;
IF "TON_60s".Q THEN
    "TON_60s"(IN := FALSE, PT := T#60s);  // reset
    "Clock_60s_IE" := TRUE;
END_IF;
"TON_60s"(IN := TRUE, PT := T#60s);

Or, more cleanly, instantiate a TP (pulse timer) with PT = T#60s and trigger it on its own Q output for a free-running 60 s pulse. Alternatively, use the S7-1200 Time-of-day clock and derive a pulse from the seconds field for sub-second precision.

Verification Procedure

1. Online tag monitoring. Open the tag table in TIA Portal, click Monitor all. Confirm:
   • %M1.2 reads 1 in STOP and RUN.
   • %M1.0 reads 1 momentarily after STOP→RUN, then 0.
   • %M20.1 alternates between 0 and 1 once per second.
2. Force / trigger test. Right-click the clock bit and select Modify operand with trigger. The trace must show a 1-second period within ±5 % tolerance (CPU scan time impact).
3. Diagnostic edge test. Insert a programming error that triggers a diagnostic event (e.g., unplug a signal module). M1.3 must pulse high for one scan; capture it with a rising-edge contact and a retentive coil for offline inspection.
4. Cross-reference audit. Run Cross-references → All on the SM tags. Every usage must show the new M-address.
5. Cycle-time impact. Open Online & Diagnostics → Cycle time. Enabling system and clock memory adds a negligible overhead (≤ 0.1 ms typical) and must not push the OB1 cycle above the configured maximum cycle time.

Troubleshooting Matrix

Edge Cases and Field-Commissioned Caveats

• Firmware < V4.0: System and Clock Memory parameters are exposed under CPU Properties → General → System and Clock Memory with a slightly different layout. The bit semantics are identical.
• Optimized block access: If the FB/FC is set to "Optimized" (the S7-1200 default), the M-byte region is NOT used for the block's local stack. The conflict warning in this guide only applies to legacy blocks with "Standard" (non-optimized) access.
• Multi-instance DBs: When a multi-instance FB chain uses MB1 / MB20 as internal scratch, the system-memory write corrupts instance data. Always confirm that no multi-instance DB touches the selected system/clock byte.
• Retentive behavior: System memory bits are NOT retentive; they reset at every STOP→RUN transition. If the application required SM0.1 to set a retentive flag, an explicit M-bit with retentive attribute must be latched from M1.0.
• OB100 / OB101 startup: The first-cycle bit M1.0 is asserted during the first scan of OB1. If the application expects first-scan behavior in the warm-restart OB100, use the OB100's local startup mode flag instead.
• HMI references: If an HMI panel (e.g., KTP1200, Comfort Panel) used to display SMB0.0 directly, the connection must be re-pointed to %M1.2 in the HMI tag database.
• Migration of S-operand (S7-200 S-bit): S7-200 S-bits (S0.0, S0.1, etc.) are also called "Set bits" and have no S7-1200 equivalent. The S7-200 S-stack must be reconstructed as a sequencer using a GRAPH FB or as a state machine in SCL.
• MW0 in first block conflict: Engineers porting programs that use MW0 (or any overlapping word) as the first temporary word in an FB/FC must select a different system-memory byte; MB1 / MW0 conflict is the most common first-scan data corruption source after a partial migration.

Companion Conversion: Other S7-200 Memory Areas

While this guide focuses on SM0.0 / SM0.1 / SM0.5, a complete S7-200 → S7-1200 conversion often requires remapping additional areas:

Verification Checklist

• ☐ System Memory Byte enabled and byte selected (MB1 recommended).
• ☐ Clock Memory Byte enabled and byte selected (MB20 recommended).
• ☐ Every SM symbol re-addressed to a valid M-bit in the PLC tag table.
• ☐ All unresolved tags resolved (compile = 0 errors).
• ☐ Cross-references updated.
• ☐ Online test confirms M1.2 = 1 in STOP and RUN.
• ☐ Online test confirms M1.0 = 1 for one cycle after restart.
• ☐ Online test confirms M20.1 (or mapped bit) toggles at expected period.
• ☐ HMI tag database updated.
• ☐ Retentive and FB-stack conflicts resolved.
• ☐ Cycle time within budget after enabling system/clock memory.