CPU 314C-2DP High-Speed Counter with Zero Mark Reset

Overview

The SIMATIC S7-300 CPU 314C-2DP integrates four on-board 24 V high-speed counters as a technological function of the CPU itself. The standard MLFB 6ES7314-6CF02-0AB0 (and successor variants 6ES7314-6CG03-0AB0, 6ES7314-6CH04-0AB0) deliver four hardware counters with a maximum input frequency of 60 kHz per channel, integrated encoder power supply (typically via the front connector X2), and digital outputs for direct actuator control.

Each counter channel uses three physical digital inputs at the front connector:

• Track A – primary counting pulse
• Track B – direction reference / second pulse train in quadrature
• Track R – zero mark (also called reference point)

The four counters can each be configured independently for one of the following technological operating modes:

The distinction between counting and position detection is central to this article: only modes 4-7 (position detection) react to the zero mark with a configurable reset or load behavior.

Encoder Signal and Counting Requirement

The encoder in question delivers:

• 20 pulses per revolution on track A
• 20 pulses per revolution on track B (phase-shifted 90°, quadrature)
• 1 R pulse (zero mark) per revolution

With 1× evaluation, the counter advances 20 counts per revolution. With 2× evaluation, 40 counts. With 4× evaluation (recommended for direction discrimination), 80 counts per revolution.

The required behavior is:

1. Count up on rising and falling edges of A and B (4× quadrature).
2. On every R pulse, reset the counter back to 0.
3. Direction detection: count up when A leads B, count down when B leads A.

Per the SIMATIC S7-300 CPU 31xC Technological Functions manual, this behavior is not achievable with SFB44 (counting). The R signal in modes 0–3 only generates a separate count of zero-mark events; it does not reset the main counter value.

Counting vs Position Detection: Why a Zero-Mark Reset Requires SFB45

In modes 0–3 (counting), SFB44 exposes the zero mark only as a diagnostic event. The value at the encoder feedback is not cleared on the R pulse.

In modes 4–7 (position detection), SFB45 (POS_CTRL) exposes a configurable reaction to the zero mark:

• Current value can be reloaded with a home position setting (parameterized in HW config).
• The POS_CYCL / ENCODER_VALUE output reflects the corrected position.
• The diagnostics SFB46 reports each zero-mark event through a status bit.

Configuring the channel as position detection, combined with the home position = 0 parameter, produces the exact behavior requested: count forward on quadrature edges, snap to 0 on every R pulse.

Prerequisites

Before commissioning, ensure the following items are available:

Reference documentation: SIMATIC S7-300 CPU 31xC Technological Functions manual (Siemens Industry Online Support entry ID 12429336 family).

STEP 7 Hardware Configuration of the Counter Channel

Open the hardware configuration (HW Config in STEP 7 / TIA Portal device view), select the CPU 314C-2DP, and open the Properties dialog of the CPU. Switch to the Counting tab and click Properties for the channel to be used (Channel 0–3).

Step-by-step configuration

1. Operating mode: select Position detection with HW gate (mode 5) if you need an external input to enable the channel, or Position detection continuous (mode 4) if you only need software enable.
2. Signal evaluation: select Single evaluation (20 pulses/rev), Double evaluation (40 pulses/rev), or Quadruple evaluation (80 pulses/rev). For tight speed control or accurate reset, quadruple evaluation is recommended – the zero mark still fires once per revolution.
3. Input filter: choose a filter constant that matches the encoder pulse width. Default 0.5 µs for fast encoders; raise to 2.5 µs if noise is suspected. Maximum input frequency must stay below the resulting threshold (f_max=1/T_filter).
4. Gate function / Load value: enable HW gate. The HW gate is a dedicated digital input on the CPU; mapping is set via the Inputs sub-tab (typically DI+0.0 / DI+0.1 / DI+0.2 / DI+0.3, one bit per channel).
5. Zero mark processing: enable the zero mark. Under Behavior on zero mark, set Home position = 0 (or another chosen reference) and choose Reset counter to home position.
6. Direction control: enable Direction reversal only if the engineering convention differs from physical rotation. With 4× evaluation, A leading B = up-count, B leading A = down-count.
7. Outputs: the integrated DI outputs (channels 0–3 each have a DO trigger output) can be configured here, e.g. compare-value triggers for limit events.
8. Save and compile the HW config, then download to the CPU.

SFB45 (POS_CTRL) Call from the Cyclic OB

In OB1 (or OB35 if deterministic timing is required), instantiate SFB45 once per used channel. Use the hardware identifier (HW ID) of the technological object visible in HW Config under System constants as the symbolic LADDR input – not the absolute I address.

// SFB45 - POS_CTRL for position detection channel 0
// LADDR = HW identifier of counter channel
// SW_GATE = enable from HMI or machine sequence

        CALL  "POS_CTRL",  DB45      // instance DB generated by SFB
        LADDR  := "Chan0_HWID"        // auto-populated system constant
        SW_GATE:= M0.0                // software gate bit
        CONTROL_INTERFACE := DB45.CI  // pass-through control structure
        ENO    := 

SFB46 (POS_DIAG) can be called at a lower priority to surface the ZERO_MARK_REACHED bit and the actual zero-mark count since last reset:

        CALL  "POS_DIAG",  DB46
        LADDR  := "Chan0_HWID"
        ENO    :=

Key inputs/outputs of SFB45

Hardware Gate vs Software Gate

Both gates must be TRUE for the counter to advance.

Behavior on rising/falling edges depends on the operating mode:

• Continuous modes 4/0: gate controls counting freely.
• Single modes 5/1: a rising edge of the SW or HW gate starts a counting sequence that ends after the configured single-cycle length, the next zero mark, or a falling edge of the gate (depending on sub-parameters).
• Periodic modes 7/3: the gate can re-arm counting periodically.

For the requested forward-count + zero-reset use case, mode 4 (continuous position detection) with the SW gate driven from the operator panel keeps the logic simplest: the moment SW gate rises, the encoder free-runs, counts up/down on quadrature edges, and resets to 0 on each R pulse.

Verification and Diagnostics

1. Open Monitor & Modify or VAT in STEP 7. Add the ENCODER_VALUE of SFB45 (DB45) to a watch table.
2. Turn the encoder slowly by hand. Observe that each full turn brings the display back to a value near 0.
3. Verify the LED on the CPU. The SF LED must be off. The RUN and STOP LEDs indicate CPU state. Channel-specific LEDs do not exist for counter channels on the CPU face – use STS_RUN in software.
4. Force the SW gate high and verify STS_RUN = TRUE in the watch table.
5. Cross-check by counting theoretical pulses: at 4× evaluation, 80 pulses per turn × 1 turn = 80 counts, peak position. The intermediate value should never exceed this unless the encoder double-pulses.
6. Verify the gate wiring with the counter status bit – if SW gate = TRUE but STS_RUN = FALSE, the HW gate on the DI is missing (count wiring broken or DI not configured).

Diagnostic IDs from SFB44/SFB45

For a complete diagnostic map refer to the Diagnostics appendix of the SIMATIC S7-300 CPU 31xC Technological Functions manual.

Troubleshooting Matrix

Field Commissioning Notes

• The 24 V encoder supply on the CPU can source at most 500 mA total across all channels. If multiple encoders draw significant current, power them from an external 24 V source.
• Encoder cables must be shielded and grounded at one end, ideally at the cabinet entry plate. Pigtail grounding is unacceptable.
• Maximum input frequency is specified per channel; using all four channels at 60 kHz simultaneously is supported by the 314C-2DP silicon but contributes to CPU execution time (~0.6 ms typical scheduler overhead in OB1). Always check the OB1 execution with a worst-case scan.
• If a fail-safe variant is used (CPU 314F-2DP), the technological functions are identical, but the safety layer must be configured separately and the encoder signals routed into both channels (see the F-CPU technical documentation).
• For higher input frequencies, migrate to the CPU 317-2 DP/PN combined with an external FM 350-1 or ET 200S counter module. The integrated counters of the 314C-2DP are limited to 60 kHz.

Differences from SFB44 (COUNT)

SFB44 (CNT_CTL) is the correct block for pure counting, frequency measurement, and pulse-width modulation. It does not support the zero-mark reset. Attempting to use SFB44 for the requirement described in this article results in:

• Counter increments freely on A/B quadrature
• A separate status register STS_ZM_FWD / STS_ZM_BWD toggles once per revolution, but the main counter value is unaffected
• Value rolls over at the configured upper count limit, regardless of the zero mark

Migration from SFB44 to SFB45 requires only that the HW configuration be switched to a position-detection operating mode. The SFB call signature changes – COUNT_VALUE becomes ENCODER_VALUE and a new CONTROL_INTERFACE struct is required.

Scaling to a Larger System

For a multi-revolution absolute position, drive the SFB45 instance to SFB PRE_PROC or write to a CFC chart. Keep the I/O scan deterministic by placing the SFB45 call in OB35 (cyclic interrupt, e.g. 10 ms) instead of OB1 if the application allows. For high-speed deterministic reading of the position without program cycle jitter, use the integrated hardware interrupt of the CPU 314C-2DP – connect a zero-mark event to OB40 (hardware interrupt) for precise capture.

FAQ