CS1G Work Bits and Timer TT Flag: AB to Omron Migration

Overview

Engineers migrating ladder logic from Allen-Bradley (AB) SLC 500 and PLC-5 platforms to the Omron CS1G face two recurring hurdles: finding an equivalent to the AB B3 internal binary bit file, and replicating the AB I:T4/TT "timer timing" flag on an instruction that, by default, only exposes a DN "done" flag. This reference documents the correct memory areas for the CS1G CPU, the difference between TIM (BCD) and TIMX (binary) instructions, how to derive a TT-style timing bit from the standard instruction set, and when a custom function block timer becomes viable. Verification steps are provided for Omron CS1G/CS1H Overview hardware equipped with CX-Programmer 6.0.

CS1G Hardware and Memory Architecture

The CS1G is a single-rack modular PLC in the CS-series family. The platform shares its instruction set and I/O bus with the higher-density CS1H and with the later CJ1/CJ2 families, which means memory areas described here also apply to most CJ1M and CJ2M replacements that have superseded the CS1G in current Omron catalogs (see the From CS1G/H to CJ2 Replacement Guide).

The CS1G CPU42 (one of the devices most commonly in service today) implements the full W, H, and D areas, with reserved CIO ranges reserved for optional I/O racks. The CS1G does not expose any EM bank; only CS1G-H and CS1H variants ship with E-area memory. When CX-Programmer 6.0 promotes the E0 area in the symbol table for an EM-configured project, confirm the target CPU is a CPU6x or higher before relying on those addresses.

Mapping Allen-Bradley B3 to Omron Work Bits

In RSLogix 500, the B3 binary file is a 16-bit word file whose individual bits are used as internal coils that never drive physical outputs. There is no hardware behind B3; it is purely a scratch space for rung logic. In Omron CS1G, the closest equivalents are:

Recommended work-bit allocation strategy

For new CS1G projects under CX-Programmer 6.0, use the PLC menu Automatic Allocation option and let the tool bind symbol names to a continuous block of W-memory. A reasonable baseline is:

1. Open the project properties dialog and confirm the target CPU is set to CS1G-CPU42 (or CS1G-CPU43/44, if installed).
2. From the PLC menu, select Automatic Allocation.
3. Specify a starting W-word of, for example, W100 and a length of 200 words (W100.00 through W211.15).
4. Bind every internal coil variable to the automatically generated address.
5. Reserve W0 through W99 for explicit hand-assignment (system-style flags) and W500 through W511 for utilities (one-shot, edge-detect, fault latches).

Using unused CIO addresses for work bits

If I/O cards occupy slots 0, 1, and 2 only, every word from CIO 3 upward is unused as a physical I/O image and can be reused as internal scratch. For a CS1G with three populated slots:

• First unused word: CIO 3 .. CIO n, where n = last_word_of_last_slot + 1.
• Beyond CIO 50, addresses are typically reserved for high-density I/O units and for the optional rack (200-word area for an Expansion Rack).
• For network slaves on Controller Link or EtherNet/IP, addresses in the range CIO 1500 + are allocated by the routing table; verify routing on the I/O Table tab.

Using CIO work bits is correct and is supported in CX-Programmer 6.0. The risk is collision: always confirm the I/O Table window shows no entry between the slot boundary and the word you intend to borrow.

Omron Timer Instructions: TIM, TIMX, TIMH, TIMHX

The CS1G timer family offers four BCD-based (TIM, CNT, TIMH, TTIM) and four binary (TIMX, CNTX, TIMHX, TTIMX) instructions. The difference is data representation:

The TIM family is supported on every CS1G unit version. The TIMX family was added later and is supported on CS1G-CPU42 with unit version 2.0 or higher. To check the unit version in CX-Programmer 6.0, open the PLC properties dialog and read the Unit Version line; it is reported in the online connection dialog as well.

Why Omron timers do not expose a TT bit

In AB, a T4:1 timer block has three flags exposed in the data table:

• TT — "Timer Timing" bit. Energized while the enable input is true and PV has not reached 0.
• DN — "Done" bit. Energized when PV reaches 0.
• EN — "Enable" bit. Energized while the timer instruction is enabled.

On the CS1G, the instruction does not allocate three flags. Instead, the timer number is the Done bit. The ladder mnemonic TIM 0001 #0100 creates a timer with PV preset 100 (10.0 s in TIM; 100 × 0.1 s) and the boolean coil T0001:

• T0001 becomes "1" when PV reaches 0 (analogous to DN).
• T0001 returns to "0" when the input condition changes from ON to OFF and the timer is reset.

There is no built-in TT-bit exposed by the instruction; the timer is implemented as a single-word current value (PV decremented each scan) and a single Done flag equal to the timer address.

Building a TT-Style Timing Bit from Stock Instructions

Because the CS1G timer lacks a native TT flag, derive one in ladder logic with two contacts and one coil:

|  --[ Enable contact ]--+--[ NOT T0001 ]--( T0010:1_TT )--|
|                        |                                    |

In words: energize an internal relay (call it TT_Flag_001 on W200.00) whenever the timer's enable input is true and the timer's Done bit (T0001) is false. This pattern repeats the exact AB semantics:

• When Enable is OFF: TT_Flag clears, timer resets.
• When Enable is ON and PV has not reached 0: TT_Flag is ON.
• When Enable is ON and PV equals 0 (Done): TT_Flag is OFF (gated by the NOT T0001).

Ladder snippet for a 5-second on-delay with TT output

|        Enable             T0001                W100.00        
|----[ / ]------------------[ ]--+---------------( )---<TT output>
|                               |
|        Enable                 |
|----[ ]--+--[ NOT T0001 ]--( W100.00: TT_latch )--|
          |                                       |
          +--<TIM 0001 #0050>--------+            
                                  ( T0001: Done )

Reading rung 1: TT_latch = Enable AND NOT Done, which is precisely the AB T4:1/TT expression. The symbol name W100.00 is not a CS1G-only artifact — it is a work bit. Most programmers bind it to a symbolic tag such as TT_T001 for readability.

Function-Block Timer for CS1G-CPU42 and Newer

If the project uses a CS1G-CPU42 with unit version 3.0 or higher, user-defined function blocks are supported. A function-block timer can encapsulate the Enable / Done / Timing / Elapsed / Remaining interface in a single named block, bringing the CS1G closer to AB's data-table exposure.

Function-block header (CX-Programmer 6.0)

Function-block body (ladder inside the FB)

1. Inside the FB, place TIMX 0001 &0 (or TIM 0001 #0 for BCD).
2. Set the timer's PV to the Preset input via a BSET or MOV instruction: MOV(021) Preset D100, where D100 is the timer PV word.
3. Implement TT as TT := Enable AND NOT TIMER_DONE. In ladder this is one N.C. contact on the timer-done flag in series with the Enable input.
4. Implement Elapsed as Preset - Remaining_PV_Counter, where the counter value is read from the timer's PV word (D100 in step 2).

Drop the FB into any rung where an AB TON or TOF would have been used. The visible interface matches the AB timer data table, so the rest of the program remains readable to engineers trained on RSLogix 500.

CS1G-CPU42 Specific Configuration

The CS1G-CPU42 is among the most-deployed CS1G units. Confirm the following before programming the timer section:

If the project targets a CPU42-H or later (CPU43, CPU44, CPU45), the W, H, and D areas all expand and the EM bank becomes available. The replacement path from CS1G to CJ2 retains the same memory map, allowing cut-and-paste of symbol tables across hardware migrations (per the From CS1G/H to CJ2 Replacement Guide).

CX-Programmer 6.0 Configuration

CX-Programmer 6.0 is the current-generation IDE for the CS1G. Use the configuration sequence below to align the IDE with the binary timer and FB work required.

1. Set the device type: In the Change PLC dialog, select CS1G, then CPU model CPU42. The device-type selection changes the online Transfer Setup dialog options.
2. Confirm online connection type: Serial (RS-232C to peripheral port) or USB-serial converter. Configure baud to 9 600 or 115 200 (default in CX-Programmer 6.0 for new projects).
3. Allocate symbol table area: From PLC > Automatic Allocation, ensure the entire W area is selected for automatic assignment. Re-run after major edits to keep contiguous allocation.
4. Enable Binary Mode for timers (optional): From PLC > Binary Operation, ensure the project is set to binary. This is what makes TIMX use the & prefix correctly without errors at compile.
5. Insert function blocks: If unit version ≥ 3.0, from Insert > Function Block > New FB. The header editor accepts BOOL, INT, DINT, and REAL data types directly.
6. Compile and download: Use PLC > Transfer > To PLC. On first download, the IDE prompts to overwrite the symbol table; respond Yes if the source of symbols is the local PC.
7. Online monitoring: Switch to Monitor Mode; the TT bit assigned to W100.00 will animate when Enable is high and PV has not yet reached 0.

For online connection via Ethernet (CJ1W-ETN21 or CS1W-ETN01), see the CS1G, CS1H Overview/Manual for IP routing and FINS node setup. The Omron CS1G does not have a built-in Ethernet port; an Ethernet unit is required.

Verification

After the rung is online, run the four verification checks before sign-off:

1. Static work-bit verification — Force W100.00 ON and OFF in Force Set / Reset dialog. Confirm that no real output (CIO 100.00+, CIO 200.00+) changes state. If an output toggles, the allocation has collided with hardware I/O; re-run Automatic Allocation and select a fresh W range.
2. TT rising edge — Energize the Enable input and place the cursor on W100.00; the address should turn ON within one scan of Enable becoming true. Decrement watch Elapsed value to confirm the timer is counting.
3. TT falling edge — Allow the timer to expire. Watch T0001 turn ON and W100.00 turn OFF in the same scan (within ±2 scans is acceptable; if visible delay grows beyond two scans, check for retentive reset on TIMER_DONE contact).
4. Reset behavior — Drop the Enable input. Both T0001 and W100.00 should clear. The TIM family automatically resets its current value to preset when Enable goes low.
5. Power-cycle retentive test — If the timer uses H-area work bits instead of W, cycle PLC power and confirm the TT pattern continues to evaluate correctly without leaving a stale ON in W100.00.

Troubleshooting Matrix

Migrating Existing AB TIM Logic

When porting a full AB routine, the side-by-side mapping below lets you translate rung logic directly without rewriting the structure.

The transition is mechanical once the two patterns above are in place. Many engineers create a small migration spreadsheet: column A is the AB tag, column B is the W-bit TT-latch destination, column C is the boolean Done flag. Once populated, an offline transfer-and-rename pass in CX-Programmer completes the bulk of the work.

Working with the CJ Replacement Path

For shop floors standardizing on the CJ2, the same memory map applies (see From CS1G/H to CJ2 Replacement Guide). The replacement guide covers migration of:

• CIO area boundaries (CJ2 has more reserved words for built-in I/O and serial port on the CPU itself).
• DM area boundaries (CJ2 retains D0 .. D32767 and adds E0_0 .. E_ as needed).
• Cycle time impact (CJ2 is faster, so a 100 ms TIM may complete in fewer scans on the new CPU — verify any application logic that depended on minimum cycle counts).
• Function block portability: CS1G FBs port directly to CJ1 and CJ2 because the instruction set is shared.

When commissioning a CS1G project on a CJ2 spare, transfer the project to CX-Programmer 9.x or later, change the target device to CJ2M-CPU3x, recompile, and download. The TT pattern in ladder is preserved unchanged across the migration, and FB-based timers continue to work without code edits.

Field-Proven Tips

1. Always reserve W500 through W511 for fault latches and one-shot utilities so the rest of the W range can be safely re-allocated by Automatic Allocation after major edits.
2. Use a separate function-block instance per "logical" timer — never reuse a single FB instance to time two unrelated processes. AB engineers often instantiate one T4 file per process; the same practice makes ladder reviews faster.
3. When documenting TT-flag rungs, include the comment // AB-equivalent: I:Tn/TT next to the contact so future maintainers can map the Omron back to an AB reference. This is especially valuable on shop floors where both AB and Omron controllers coexist.
4. If the panel uses CS1G plus a non-Omron HMIs (e.g., Pro-face), see the third-party Host Link driver CS/CJ Series HOST Link Driver for FINS protocol details.
5. Keep a printed copy of the W-area allocation on the inside of the cabinet door. Updates from Automatic Allocation in CX-Programmer 6.0 silently shift addresses; the printed map is the only ground truth the maintenance technician has at the panel.

FAQ