Where does the position signal travel?
Follow the complete electrical path before selecting protection. The laboratory prototype uses a 10 kΩ multiturn potentiometer to represent the field sensor. The measurement then reaches the PIC18F2423 ADC, passes through the position-scaling logic, and appears on an S401C52TR static-drive LCD through a PCF85162 display driver.
The field wiring is not yet defined well enough to treat it as a single conductor carrying a voltage. If the final sensor is a passive potentiometer, the panel sends excitation and return conductors to the valve and receives the wiper voltage on a third conductor. Cable resistance, connector resistance, excitation stability, and return-current voltage drop all enter the measurement. If the final sensor is an active voltage-output device, document its supply, output impedance, reference conductor, allowable load, and common-mode range.
| Path element | Required design input | Failure to detect |
|---|---|---|
| Sensor | Passive or powered; output range; source impedance | Incorrect scaling or ADC acquisition error |
| Field cable | Length, conductor resistance, pair arrangement, shield, route | Noise pickup and position-dependent error |
| Reference conductor | Expected ground-potential difference and fault current | ADC overvoltage despite a valid signal voltage |
| Panel connector | Surge-current diversion path | Transient current crossing the logic ground plane |
| ADC input | Absolute input limits, leakage budget, acquisition time | Damage, clipping, or code-dependent conversion error |
Layer one first: measure the installed cable resistance, conductor-to-conductor capacitance, conductor-to-shield capacitance, shield termination, and maximum difference between the sensor return and panel reference. Those measurements decide whether a protected voltage input remains practical.
Which transmission architecture fits the power constraint?
Three approaches address the tens-of-meters path. They move the vulnerable high-impedance node to different locations and impose different energy costs.
| Approach | Long cable carries | Principal advantage | Principal cost or limitation |
|---|---|---|---|
| Protected voltage input | Analog voltage and reference | Lowest change from the validated prototype and potentially the lowest average current | Sensitive to coupled noise, cable leakage, source impedance, and ground-potential difference |
| Remote ADC with digital link | Differential digital traffic | Converts the position near the sensor; CRC and retransmission can detect corrupted messages | Requires field electronics, a second controller, transceiver energy, surge protection, and a defined communications protocol |
| 4–20 mA loop | Current signal | Rejects many voltage-drop and coupled-noise problems that affect high-impedance voltage signals | Conflicts with the stated ultra-low-power objective if the battery must continuously supply the loop |
A 3.6 V logic rail does not make a 4–20 mA interface categorically impossible. Logic voltage and loop compliance voltage are separate design quantities. An externally powered loop or a power-conversion stage can interface with low-voltage logic, provided the loop has enough compliance for the transmitter and wiring. The power budget remains the deciding constraint.
At 3.6 V, the prototype's measured 0.4 mA average represents approximately 1.44 mW. A continuously battery-supplied loop would draw at least the signal current itself: ten times the prototype current at 4 mA and fifty times at 20 mA, before conversion losses. With an 8500 mAh cell, the ideal capacity-only figures are about 88.5 days at 4 mA and 17.7 days at 20 mA. They are not field-life predictions.
Retain the voltage architecture only after the cable and ground measurements demonstrate adequate margin. If they do not, place the ADC near the sensor and use a protected differential digital link such as RS-485. Transmit short request-and-response bursts, include a CRC, reject invalid frames, request retransmission, and place the controllers and transceiver into low-power states between samples.
Why does a long voltage input become unstable or fail?
| Observed symptom | Likely mechanism | Discriminating check |
|---|---|---|
| Displayed position changes when a motor, VFD, or relay operates | Capacitive or inductive coupling into the signal or reference conductor | Capture the connector voltage and ADC-side voltage during the switching event |
| Stable reading in the laboratory but an offset in the field | Cable resistance, return-path voltage drop, leakage, or ground-potential difference | Measure excitation, return, and wiper voltages at both ends under operating conditions |
| Reading clips at zero or full scale | Protection clamp conduction, ADC rail violation, open wire, or shorted conductor | Measure before and after the series input resistor and inspect clamp current |
| Intermittent reset or permanent ADC error after a storm | Lightning-induced common-mode or differential transient entering through field wiring | Inspect the surge-current path and reproduce the defined surge test at the connector |
| Slow drift or nonlinearity after adding protection | TVS leakage, board contamination, resistor error, or insufficient ADC acquisition time | Test input leakage and conversion error across temperature and input range |
A voltage amplitude can remain nominal while its common-mode voltage exceeds the ADC limits. Differential noise appears between signal and return; common-mode noise moves both conductors relative to the panel electronics. Protection and testing must address both cases.
How should the connector and ADC input be protected?
Place the first transient-diversion device at the field connector. A long trace from the connector to the clamp adds inductance and lets the internal node rise during a fast event. Route surge current toward the intended chassis, enclosure, or reference connection without forcing it through the MCU and display return paths.
- Select a TVS whose normal standoff range does not conduct at the highest valid sensor voltage, including tolerance and fault conditions.
- Check its clamping behavior against the ADC-side network rather than treating its nominal marking as the protected voltage.
- Add series resistance after the connector-side clamp to limit current reaching the ADC and any secondary rail clamps.
- Add the RC filter on the protected side of the series impedance.
- Verify that resistor tolerance, TVS leakage, ADC leakage, and board leakage stay within the position-error budget.
- Check the resistor's transient energy and voltage stress during the selected surge test.
For a slow analog position input, low capacitance is not the only TVS selection criterion. Leakage over temperature can create a larger DC error than capacitance, particularly with a high source impedance. Capacitance still affects filter cutoff and settling. Select from the maximum valid voltage, required clamp level, surge waveform, leakage, capacitance, and repetitive exposure ratings stated in the component data.
A PCB-mounted TVS cannot make the instrument survive a direct lightning strike. Lightning-induced transients on nearby wiring are a testable design case; a direct strike requires installation-level bonding, routing, and protection decisions outside the ADC network.
How should the cable and filter reject EMI?
Run the signal with its reference as a pair so coupled fields affect both conductors similarly. Keep the pair away from VFD output conductors, motor feeders, and switched relay wiring. Define the shield connection from the installation grounding plan; an undefined shield termination can become either an antenna or an unintended current path.
Set the analog low-pass filter from valve motion and sampling requirements. For a first-order RC network:
f_c = 1 / (2πRC)
Choose f_c above the highest position-change bandwidth that must be displayed and below the unwanted high-frequency content. Then select the sampling rate and digital averaging so they do not alias remaining interference into the indicated position. A valve indicator usually does not require a high update bandwidth, but the required response time must come from the control and safety requirements rather than an assumed value.
Large series resistance improves transient current limiting but increases settling time and interacts with the ADC's internal sampling capacitor. Verify acquisition time at the highest source resistance and across the full input range. If a buffer is required, include its input common-mode range, rail behavior, offset, bias current, quiescent current, and startup time in the battery and accuracy budgets.
How should the battery and power stage be designed?
The capacity-only life estimate is:
This is an ideal calculation, not a service interval. Build the field estimate from cell capacity at the operating temperature and load profile, self-discharge, sleep current, display current, sampling bursts, communications bursts, regulator loss, protection leakage, end-of-life voltage, and the MCU's brownout threshold. The cell chemistry was not specified, so read these values from the selected cell datasheet.
Use reverse-polarity protection that preserves the limited voltage margin. A series diode is simple but consumes forward voltage continuously; a MOSFET-based reverse connection stage can reduce that drop. Add fault-current limiting appropriate to the cell's available short-circuit energy. Verify startup with a depleted cell and the worst simultaneous display, measurement, and communications load.
For an oil-and-gas installation, identify the area classification before freezing the battery, enclosure, connector, protection capacitance, or energy-storage components. Requirements must be traced from classification and system requirements to schematic implementation, component evidence, and a specific test result.
Which immunity tests belong in the requirements?
Use IEC 61000-4-5 as the reference document for surge-immunity planning and IEC 61000-4-4 for electrical fast-transient/burst immunity. The required test levels, coupling method, ports, performance criteria, and acceptance behavior must come from the product's applicable compliance plan; the document number alone does not define a passing design.
| Requirement group | Design evidence | Verification record |
|---|---|---|
| Surge and lightning-induced transient | Connector clamp, current path, component stress calculations |
IEC 61000-4-5 test configuration and observed behavior |
| Fast switching disturbance | Cable layout, RC network, grounding and shielding plan |
IEC 61000-4-4 burst test and position-error log |
| ESD | Accessible-point discharge path and clamp selection | Defined contact and air-discharge test results from the compliance plan |
| Reverse battery | Polarity-protection schematic and stress analysis | Reverse connection test with recorded current and recovery |
| Signal faults | Current limiting and diagnostic behavior | Open, short, rail fault, and miswiring tests |
How is the design verified before field release?
- Replace the simulated sensor with the final sensor and production-equivalent cable, connector, shield, and grounding arrangement.
- Record voltages at the sensor, panel connector, protected ADC node, and MCU supply at minimum, midpoint, and maximum position.
- Operate nearby representative VFD, motor, and relay loads while logging raw ADC codes, displayed percentage, resets, and communication errors.
- Apply the defined surge, burst, ESD, reverse-polarity, open-wire, short-circuit, and miswiring tests. Inspect both function and latent parameter drift after each exposure.
- Repeat accuracy, leakage, startup, and battery-current measurements over the required environmental range.
- For a digital alternative, inject corrupted and missing frames; confirm CRC rejection, timeout behavior, retransmission, and recovery without displaying a false valid position.
- Calculate battery life from the measured duty-cycle current profile and the selected cell's usable capacity at the limiting temperature and end voltage.
- Close every requirement with a schematic reference, calculation or component rating, test method, recorded result, and acceptance decision.
FAQ
Can I send a valve position voltage tens of meters?
Yes, if cable resistance, leakage, coupled noise, ground-potential difference, and surge exposure fit the error and stress budgets. Measure both ends of the installed signal and reference conductors before approving the architecture.
Does 3.6 V logic make a 4–20 mA loop impossible?
No. Logic voltage and loop compliance are separate, but a battery that continuously supplies 4–20 mA conflicts with the measured 0.4 mA average-current target unless an external loop supply changes the power architecture.
Can a TVS diode protect the ADC from lightning?
A correctly selected connector-side TVS, series impedance, and controlled surge-current path can protect against specified lightning-induced transients. It is not a complete defense against a direct lightning strike.
Does an RC filter change the indicated valve position?
It changes response time and can introduce settling error if the ADC samples too soon. Calculate f_c = 1/(2πRC), then verify full-scale accuracy and acquisition time with the final sensor and cable.
Can I release the design after it passes laboratory accuracy tests?
No. Repeat accuracy after IEC 61000-4-5 surge, IEC 61000-4-4 burst, ESD, wiring-fault, polarity, environmental, and battery tests; approve release only after the final production-equivalent assembly passes the recorded acceptance criteria.