ET 200SP AI 6ES7134-6HB00 Update Time: S7-1500 TIA Configuration

Technical reference for the SIMATIC ET 200SP AI 2×U/I 2-/4-wire HS analog input module (order number 6ES7134-6HB00-0CA1). Covers default update time, sample/conversion timing, peripheral-access reads (IWn:P), FC / FB design patterns, integration-time trade-offs, isochronous PROFINET configuration, and TIA Portal commissioning checks for S7-1500 controllers.

Module Identification and Scope

The order number 6ES7134-6HB00-0CA1 identifies the SIMATIC ET 200SP AI 2×U/I 2-/4-wire HS (High Speed) analog input module. The HS suffix designates the high-speed variant of the ET 200SP AI family with isochronous-mode support, sub-millisecond update capability, and dedicated channel-diagnostic interrupts. The module provides two channels that can each be wired as voltage (U) or current (I), in 2-wire or 4-wire connection modes, with 16-bit resolution.

Decoding the MLFB (Machine-Readable Product Designation):

• 6ES7 - SIMATIC product family identifier
• 134 - Function class: analog input module
• 6 - ET 200SP distributed I/O system
• HB - AI 2×U/I 2-/4-wire, High Speed variant
• 00 - Functional state index (firmware family)
• 0CA1 - Hardware revision / firmware version suffix

Update-Time Fundamentals: Sample, Conversion, Cycle

Three timing values govern when a value visible to the user program reflects a real electrical change at the screw terminal:

1. Sample time (t_S) - The interval at which the module's ADC samples the input signal. Shorter sample time yields wider bandwidth but increases noise pickup.
2. Conversion time (t_C) - The interval the ADC requires to digitize the sampled value. For the 6ES7134-6HB00-0CA1 in default TIA configuration, this is 10 ms per channel as confirmed in the module discussion.
3. Update time (t_U) - The interval at which the module transfers a freshly converted value to the backplane bus, refreshing the process image visible to the CPU.

The end-to-end latency seen by a function block = module update time + PROFINET update time + OB1 / OB1x cycle time. With 10 ms default and a 2 ms OB1 cycle, the program-visible latency is approximately 12 ms.

Reference: S7-1200 Signal-Board Update Times

For comparison, the S7-1200 analog signal board (SB) documentation publishes the following values, illustrating how integration frequency drives update rate:

Source: Sample time and update times for the analog inputs - TIA Siemens Documentation

The ET 200SP AI HS module extends the range significantly on the high end, supporting integration times as short as 2.5 ms / 400 Hz in isochronous mode. The exact minimum update time for the 6ES7134-6HB00-0CA1 must be verified against the module's manual because the figure varies with firmware revision and PROFINET send-clock selection.

Default Configuration: 10 ms Update Time

Out of the box, with both channels enabled at the default integration setting, the 6ES7134-6HB00-0CA1 returns a refreshed value every 10 ms. The user program sees a new value at the IW input word at each OB1 cycle, with a maximum latency of one OB1 cycle plus one module update interval.

Default configuration produces these timing values:

• Sample time per channel: approximately 5 ms
• Conversion time per channel: 5 ms
• Per-channel update time: 10 ms
• Number of channels used: 2 (scanned sequentially in multiplexed architecture)
• Effective refresh of channel 0: 10 ms
• Effective refresh of channel 1: 20 ms (multiplexed scan: channel 0, then channel 1)

Direct Value Read: IWn:P Syntax

The standard input word IWn is refreshed from the process image at the end of the OB1 cycle (or on each access for S7-1500 with automatic process-image update). To obtain the most recent hardware value immediately - bypassing the process image - Siemens provides the "P" qualifier:

IWn:P

Where:

• n - input word address (for example, IW 0, IW 2, IW 4)
• :P - "peripheral access" - direct read from the I/O module, bypassing the I/O process image

Behavior:

1. The instruction reads the most recently converted value from the module's internal buffer immediately.
2. It does not refresh the standard IWn in the process image. The peripheral read is a one-shot direct query.
3. If the same value is required in multiple places, the read result must be stored in a static or temporary variable first - the value is not cached.

Worked example in Structured Text for a function block that needs an immediate sample:

// FB 1 - "FastAnalogRead"
VAR
  aiCurrentValue : INT;    // Static - holds most recent direct read
  aiFilteredValue : REAL;  // Smoothed value used downstream
END_VAR

BEGIN
  // Read the most recent hardware value NOW (bypass process image)
  aiCurrentValue := "DI_AI_HW".%IW0:P;
  // Scale INT 0..27648 to engineering units 0.0..100.0 %
  aiFilteredValue := INT_TO_REAL(aiCurrentValue) / 276.48;
END_FUNCTION_BLOCK

The peripheral read incurs the module's internal conversion cycle, not additional bus time. A peripheral read requested 1 µs after the module's update event returns the new value; a read requested 1 µs before the next update returns the previous one. The user code cannot tell which it received without a timestamp.

FC 2 and FB 1: Reading vs. Using the Value

The original question describes a design where FC 2 collects all current physical I/O states (100 digital inputs, 20 analog inputs) and FB 1 (or other downstream code) consumes those values. Two valid implementation strategies exist, with very different timing characteristics:

Strategy A: Centralized Snapshot in FC 2

FC 2 reads the inputs (optionally using :P peripheral access) and stores them in a global DB. FB 1 reads from the DB. This guarantees consistency - all 20 analog values come from the same instant in process time - but introduces the FC 2 cycle time as additional latency.

// FC 2 - "CollectIO"
VAR_TEMP
  tInfo : SYSTEM_INFO;
END_VAR

VAR_GLOBAL
  gAnalogSnapshot : ARRAY[0..19] OF INT;  // Populated by FC 2
END_VAR

BEGIN
  // Capture 20 analog values from ET 200SP head module 0
  gAnalogSnapshot[0]  := "ET200SP_Head".%IW0:P;
  gAnalogSnapshot[1]  := "ET200SP_Head".%IW2:P;
  gAnalogSnapshot[2]  := "ET200SP_Head".%IW4:P;
  // ... continue for all 20
END_FUNCTION

Strategy B: Direct Read in FB 1

FB 1 reads the analog inputs directly at the point of use with :P access. Values reflect the module's most recent conversion but are not guaranteed to be aligned in time across the 20 channels - each :P read can return a value from a different module scan.

Integration Time and Noise Rejection

The module supports configurable integration times that trade update rate against mains-frequency noise rejection. Typical selections available in TIA Portal under the channel diagnostics view:

Select the integration time closest to 1/f of the local mains frequency for typical process measurements. Select 2.5 ms only when the application explicitly requires the bandwidth, because noise rejection degrades significantly. For settling-time theory on related DAC architectures (8 µs at 8-bit LSB settling), see the TI precision-DAC reference: Settling time and update rate - TI video and DAC - Understanding Settling Time & Update Rate - TI E2E. The same settling-vs-bandwidth trade-off applies in the input direction: shorter integration lets signal edges through faster but also admits more noise.

Isochronous Mode for Deterministic Latency

The 6ES7134-6HB00-0CA1 supports isochronous (synchronous) mode via PROFINET IRT (Isochronous Real Time). In isochronous mode:

1. The PROFINET controller sends a synchronization frame at a configured send clock - typically 250 µs to 4 ms.
2. The ET 200SP interface module distributes the sync to all slots in the station.
3. The AI module samples its inputs, converts them, and makes them available in a deterministic window - typically 1 to 2 send clocks after the sync edge.
4. Values are guaranteed to be present in the process image at a precise phase offset from the sync frame, allowing jitter-free coupling to motion or high-speed control loops.

Configuration prerequisites for isochronous mode:

• ET 200SP PROFINET interface module (IM 155-6 PN) with firmware version supporting IRT - confirm against the IM manual.
• S7-1500 CPU with firmware that supports isochronous tasks (most current S7-1500 CPUs do, but verify the catalog note).
• PROFINET topology configured in TIA Portal with a sync domain and a designated sync master.
• Port assignment: controller and device must share the same sync role configuration (sync master / sync slave).

Within TIA Portal, the path is: Device configuration → ET 200SP station → AI module → Properties → "Isochronous mode" → enable → assign the slot to a PROFINET IO system with isochronous tasks enabled.

For motion applications, the typical isochronous task is set to the servo cycle (1 ms is common) and the AI values appear with a defined Ti (input time) and To (output time) per the PROFINET plan. Field-proven caveat: the bus cycle time in the PROFINET send-clock must be a divisor of the OB1x cycle time, or TIA Portal will issue a topology diagnostic during compile.

Hardware Limit: Multiplexed Architecture

Unlike a SAR ADC with simultaneous sample-and-hold on every channel, the ET 200SP AI module is multiplexed. The analog switch connects channel 0, samples and converts it, then switches to channel 1, samples and converts, then returns to channel 0. With two channels enabled at 10 ms conversion, channel 0 has a true 20 ms effective update rate (not 10 ms), and channel 1 the same. Setting one channel to "disabled" in TIA Portal reduces the per-active-channel update time by half.

For applications requiring simultaneous sampling of all channels, the ET 200SP family provides dedicated modules (such as AI Energy Meter or RTD/TC variants with per-channel track-and-hold). The 6ES7134-6HB00-0CA1 does not have a simultaneous-sample architecture; do not assume channel 0 and channel 1 are time-aligned within one module scan.

Peripheral-Access Code Patterns

The peripheral-access qualifier is universally available in SCL, STL, LAD, and FBD for S7-1500 and S7-1200. Avoid using :P in tight loops because each call initiates a new read on the backplane bus - the I/O module services one request per cycle. For multiple channel reads, prefer the I/O address-offset form:

// Sequential channel read using pointer arithmetic (SCL)
#iValueCh0 := "ET200SP".%IW0:P;
#iValueCh1 := "ET200SP".%IW2:P;
// Both reads complete within one module scan; subsequent reads in
// the same OB cycle return cached values from the bus interface.

For 20 analog channels spread across multiple AI modules, the worst-case latency from a field event to a program-visible value is the sum of:

1. Module update interval per channel (10 ms default, ~0.156 ms isochronous at 400 Hz)
2. Bus cycle (PROFINET update time, typically 1 ms)
3. OB1 cycle or OB1x cycle time

For default 10 ms operation: 10 + 1 + OB1_typical (2 ms) = approximately 13 ms end-to-end latency. For isochronous 250 µs operation: 0.25 + 0.25 + OB1x (0.5 ms) = approximately 1 ms end-to-end latency.

Configuration in TIA Portal

Step-by-step procedure to set update time on the 6ES7134-6HB00-0CA1:

1. Open the project in TIA Portal (V16 or later recommended for full module support).
2. Expand the ET 200SP station in the project tree, right-click the AI module, choose "Properties".
3. Navigate to the "Channel 0" and "Channel 1" tabs. For each, select:
   • Measurement type: Voltage (U) or Current (I)
   • Measuring range: 0..10 V, ±10 V, 0/4..20 mA, etc.
   • Integration time: 2.5 / 16.6 / 20 / 100 ms (per the rejection table above)
4. Navigate to "Module parameters" and verify the "Diagnostics" settings for wire break and overflow.
5. If isochronous mode is required: Properties → "Isochronous mode" → enable. Then assign to an isochronous PROFINET IO system.
6. Compile the project and download hardware configuration to the CPU.
7. Online → "Monitor all" to view the live IW values and the channel status.

Diagnostics and Verification

Verification checklist for the 6ES7134-6HB00-0CA1:

1. Online diagnostics: TIA Portal → Online → Diagnostics → Module information. The "Module status" should read "OK" and "Channel status" should read "Valid value".
2. Process image inspection: Add a watch table. Force a known voltage / current on the input terminal. Confirm the IW value updates within one integration interval plus one OB1 cycle.
3. Quality code (S7-1500): Use "AI_Channel".%IW0 with quality information. The associated ST (S7-1500) or QUALITY tag indicates "Good (non-cascade)" when the value is valid; a value of 0x80 (bad) or 0x40 (uncertain) indicates a channel fault or re-initialization state.
4. Isochronous diagnostics: If isochronous mode is active, TIA Portal → isochronous tasks panel → "Life sign" must remain at zero. A non-zero life sign indicates the synchronization was lost - the application is still running but values are no longer deterministic.
5. Cycle time measurement: Insert a timer in OB1 reading the same IW. The minimum observed interval between value changes equals the integration time. If the observed interval exceeds the configured value, check the OB1 cycle time and any "process image update" settings.

Troubleshooting Matrix

Field-Proven Caveats

• The peripheral-access read IWn:P returns a value cached in the IM (interface module), not a freshly-triggered conversion. Forcing a fresh conversion requires an isochronous sync edge or a separate trigger mechanism.
• Mixed-vintage ET 200SP stations (older IM, HS AI) limit the minimum send clock. If the IM does not support 250 µs, the AI cannot deliver its fastest update either - the bus, not the module, is the bottleneck.
• For 100 digital inputs + 20 analog inputs scanned in one OB1 cycle with :P, the OB1 cycle time grows noticeably (the I/O bus serializes the reads). On a 1 ms nominal OB1, plan for 2-3 ms with the :P pattern and 1 ms with the standard process-image pattern.
• For thermal-RTD or thermocouple measurement, the 6ES7134-6HB00-0CA1 is the wrong module - select the AI 4×RTD/TC or AI Energy Meter variant. The U/I module is specified for voltage and current only.

FAQ