Geo Brick Encoder Registers: Overwritten, Not Retained

Geo Brick encoder register values that return to zero point to startup ordering, a competing writer, or another reset—not an EnDat error by itself. In the shown PLC, the control words are written before the half-second delay, leaving later initialization free to replace them.

Configuration approaches

Use a delayed one-shot write to prove the startup-order diagnosis. Then move the values into the controller's documented retained configuration mechanism, if one exists for this encoder channel. Do not use a continuously writing PLC until the identity of the competing writer is known.

Register roles and observations

The identical numeric offset in X and Y memory does not make X:$78B20 and Y:$78B20 the same register. The memory-space selector is part of the address. A changing M7505 therefore does not demonstrate that M7501 was overwritten.

Before anything else, confirm the M-variable definitions exactly as entered in PEwin32. The appearance of $38140D in an unexpected M-variable calls for a mapping audit: inspect every M-variable assigned around these addresses and check for duplicate symbols, incorrect X/Y selectors, or another definition using the same control register.

Startup overwrite mechanism

The supplied PLC performs these operations in this order: write $020003, write $38140D, wait one-half second, and disable itself. The delay does not protect the writes because it occurs afterward. Any hardware initialization, firmware setup, saved startup program, or other PLC that runs during that interval can restore a default value before PEwin32 is inspected.

A control register and a data register also have different lifecycles. Control fields may include writable configuration bits, command bits that clear after acceptance, or status fields maintained by hardware. A data register changes as protocol transactions progress and may read zero while idle. Classify each bit from the Geo Brick register description before requiring it to remain static.

The zero value at Y:$78B21 means no represented error bit is active at the instant sampled. It does not prove that $020003 and $38140D survived initialization, that an EnDat exchange occurred, or that encoder data was valid.

Delayed one-shot procedure

1. Stop other user PLCs that can address X:$78B2F or X:$78B20. Search the controller configuration for those addresses and for M7500 and M7501. Do not move on until each location has one known writer.
2. Retain the mappings exactly as separate X- and Y-space definitions:

   M7500->X:$78B2F,0,24
   M7501->X:$78B20,0,24
   M7505->Y:$78B20,0,24

3. Move the stated half-second delay ahead of the control-register writes. This places the write after the startup interval instead of exposing it to that interval:

   open plc 1 clear
   I5111=500*8388608/I10
   while(I5111>0)
   endwhile
   M7500=$020003
   M7501=$38140D
   Disable plc 1
   Close

   The calculation is the supplied controller timing expression; its half-second interpretation depends on the configured meaning of I10.
4. Immediately after PLC 1 executes, read M7500 and M7501. Confirm $020003 and $38140D before inspecting encoder data.
5. Monitor M7505 and Y:$78B21 while the application requests encoder operation. Judge M7505 as live data and decode Y:$78B21 by individual error bits rather than treating a momentary zero as a complete health test.

Reset and retention diagnosis

A power-cycle return to defaults does not identify a watchdog by itself. Direct hardware-register writes are normally volatile unless a documented retained configuration layer restores them. A watchdog reset, commanded reset, startup configuration load, or power interruption can produce the same visible result.

1. Read the controller's reset-cause or diagnostic record immediately after the unexpected restart, before issuing another reset. Use the recorded cause to separate watchdog action from an ordinary power-up or commanded reset.
2. Check whether PLC 1 is enabled automatically after power-up. The observed I5=3 confirms PLC activity at the time it is read, but it does not prove when PLC 1 ran relative to encoder-interface initialization.
3. Confirm that the project and PLC enable state were saved through the controller's documented nonvolatile-save operation. Saving a PLC program and retaining a peripheral register value are separate requirements.
4. Power-cycle once, timestamp the execution of PLC 1 if the programming environment permits it, and watch M7500 and M7501 from startup through the delayed write.

Verification and recurring pitfalls

Do not diagnose control retention from M7505, assume that zero error flags prove valid position data, or leave a fast PLC repeatedly writing hardware controls. Capture immediate readback, delayed readback, and post-power-cycle readback as three separate tests.

FAQ