The instruction picker greys out ADDBD and SUBBD the moment the PLC type is set to D2-250-1. That is the whole problem in one line: the H2-CTRIO hands you a 32-bit signed quadrature count sitting in two V-memory words, and the binary double-word math group you used on the DL06 with an H0-CTRIO is not available to consume it. Get the machine running on real-number math tonight, then decide whether the precision ceiling matters for your travel range.
Map the Counter and Prove You Can See All 32 Bits
Open CTRIO Workbench and read the input map for the slot before you write a rung. The raw count for a quadrature channel occupies a word pair. In this rack it lands at V3002, which means the low word is V3002 and the high word is V3003 (V-memory addressing is octal, so the next word up is 3003, not 3010).
Use the Workbench monitor function first, with the ladder logic irrelevant. Turn the encoder by hand and watch the count move in both directions. If it does not move here, the fault is wiring, channel configuration, or encoder power — stop and fix that before touching math.
- Read the pair with a single double-word load:
LDD V3002. - Never
LD V3002andLD V3003separately and reassemble by hand. It works until the count crosses 32767 or zero, then it lies.
Check: jog forward past 32767 counts and confirm the double word keeps climbing rather than wrapping. Jog backwards through zero. Data View showing 4294967295 instead of -1 is a display-format setting, not a fault.
Settle the Binary-Double Question Before You Write Any Math
Two claims collide here. The math chapter of the D2-USER-M is cited as covering double-word binary numbers on the 250-1, while the instruction support table lists ADDBD and SUBBDThe distinction that resolves it: the 250-1 handles 32-bitdata perfectly well (double-word load, store, move, and the BCD double-word math group). What it lacks is the binary two's-complement double-word arithmetic group.
| Test in DirectSOFT | Result | What to do |
|---|---|---|
PLC type = D2-250-1, place ADDBD/SUBBD
|
Greyed out or rejected | No binary double math. Go to the real-number path. |
| Instruction places and compiles | Accepted offline | Prove it downloads to the real CPU and the CPU enters RUN without an unsupported-instruction fault. |
Check: project PLC type is D2-250-1, the program compiles with the instructions you actually intend to use, and the download completes with the CPU in RUN.
Convert to Real and Run the Compares There
Three quick fixes get tried first and all three cost a shift. Hand-rolled 16-bit carry/borrow logic breaks at the sign boundary. BCD double-word math has no sign at all and caps at 99,999,999 — feeding it a negative binary count produces garbage. Faking the CPU type in DirectSOFT compiles and then fails at the CPU.
What runs: convert the raw binary count to a real number and keep every downstream operation in real math.
// Read the raw CTRIO count as a double word, convert to real
LDD V3002 // 32-bit raw quadrature count, low word at V3002
BTOR // binary -> real in the accumulator
OUTD V4000 // real working copy (any free double-word pair)
// Compare working position against a real setpoint stored at V4010
LDD V4000
CMPR V4010 // updates the compare status relays
// NEXT rung: act on the less-than / greater-than SP flag immediately
Do all arithmetic with the real instructions — SUBR for offsets and deltas, real compares for limits. Setpoints must be stored as reals in double-word pairs; a BCD or integer constant dropped into a real compare will not do what the rung says.
The compare status relays are shared across every compare in the program. Act on the flag on the rung immediately following CMPR, or latch it into a control relay in that same rung. Any other compare executing in between overwrites the flags. Pull the exact SP bit numbers for less-than, equal, and greater-than from the instruction chapter of the D2-USER-M rather than from memory.
Check: write a known value into the raw pair, execute the compare, and confirm only the expected flag sets.
Test the Sign Path and the Precision Ceiling
Two failures live in this conversion, and neither shows up until the machine runs backwards.
Sign. Jog the encoder in reverse through zero and watch the real working copy. A value of -2.0 is correct. A value of 4294967294.0 means the double word was taken as unsigned. Fix it by testing the sign bit — bit 15 of the high word V3003 — and subtracting 4294967296.0 from the converted value when that bit is set. Comparing two negative reals is not the problem people expect it to be; a real compare handles two negatives correctly once genuinely signed values arrive at the instruction.
Precision.Integers are exact only to 16,777,216. Past that, counts quantize.
| Count magnitude | Smallest step a 32-bit real can represent |
|---|---|
| 0 to 16,777,216 | 1 count (exact) |
| 16,777,216 to 33,554,432 | 2 counts |
| 33,554,432 to 67,108,864 | 4 counts |
| 67,108,864 to 134,217,728 | 8 counts |
If the application must resolve one count anywhere across the full signed range, the real path will not carry it. Keep the raw double word as the counting truth, and window it: use the CTRIO reset or a preset so the counter never leaves plus or minus 16,777,216, or shift the mechanical zero so the working range stays single-sign. Use the real copy for display, scaling, and limit compares.
Check: drive to the far end of travel, record the raw double word and the real copy, and subtract. Any divergence means you are above the mantissa limit and need to window the counter.
Rate Scaling: Use It for Speed, Not for Position
Workbench can scale the quadrature channel to a rate value and present it as floating point in the mapped words, which is tempting for a rung that trips on "rate less than -2". Two things decide whether that rung is legal.
- Is the rate signed? Turn the encoder in reverse and read the mapped words directly in Data View. If the module returns magnitude only, take direction from the sign of the position delta or from the channel's direction status bit and AND it with the magnitude compare.
- How much latency can the interlock tolerate? Rate is derived over a sample window inside the module. The rung responds one sample window plus one PLC scan after the event. For a reaction-time interlock, compute the delta in ladder over a fixed timer base from the raw counts — current position minus position one timebase ago, sign included — and compare that.
Check: reverse the encoder at a known speed, watch the mapped rate value and the ladder-computed delta side by side, and time the rung transition against the actual direction reversal.
Run the End-to-End Check, Then Stop
- CTRIO Workbench monitor shows the count moving both directions with the drive off.
- Data View on
V3002as a double word tracks Workbench one for one. - The real working copy tracks the raw double word through zero, into negative, and back.
- Compare flags set at the setpoint from both approach directions, with no other compare executing between the compare and the rung that uses the flag.
- Full-travel run: raw double word and real copy agree within the mantissa limit for your count range.
- Power cycle the rack. The CTRIO reloads its configuration and the map still lands where the ladder expects it.
If DirectSOFT accepts an instruction with the PLC type set to D2-250-1 but the CPU rejects it at download or faults in RUN, stop and call AutomationDirect technical support with the CPU firmware revision and the exact instruction mnemonic — that is a CPU support-table question, not something to paper over in ladder. Do the same if the CTRIO input map shifts after a power cycle, because that points at module configuration rather than logic. And if the machine truly needs one-count resolution across the entire signed 32-bit range, price the controller migration — Do-more class hardware carries signed 32-bit integers natively — instead of stacking more conversion logic onto a 250-1.
FAQ
The project compiles offline, but the D2-250-1 enforces its own instruction set and will reject the download or fault on the instruction. Set the type back to D2-250-1 and use BTOR with real-number math.
What happens if the CTRIO count goes negative and I feed it straight into BTOR?
Jog the encoder in reverse through zero and read the converted value: -2.0 is correct, 4294967294.0 means the double word was read as unsigned. Fix it by testing bit 15 of the high word (V3003 when the raw count starts at V3002) and subtracting 4294967296.0 when that bit is set.
What happens if the count passes 16,777,216 while stored in a real register?
Resolution degrades — the smallest representable step becomes 2 counts, then 4 above 33,554,432. Keep the raw double word as the counting reference and window the counter with a CTRIO reset or preset so it stays inside plus or minus 16,777,216.