How Do PWM Frequency and Current-Loop Speed Interact?

After the PWM, sensing, and timing architecture are matched, a low-inductance motor can run with controlled current ripple without executing the current regulator at every switching edge. Changing the displayed carrier frequency and deadtime alone will not make a controller designed for 20–30 kHz operate correctly at 500 kHz.

What is the switching-frequency setting telling you?

The value on the configuration screen is the requested PWM carrier frequency. Trace that value through the firmware to the timer clock, PWM period register, modulation update, ADC trigger, current reconstruction, protection logic, and gate-driver inputs. Every stage must support the resulting timing.

A 500 kHz carrier has a 2 µs period. A 20 kHz carrier has a 50 µs period, while 30 kHz has approximately 33.3 µs. The proposed frequency therefore leaves much less time for deadtime, device transitions, current-sensor settling, ADC acquisition, computation, and pulse-width generation.

What the operator sees	Likely mechanism	Measurement that separates the causes
Phase current falls to zero between PWM pulses	Discontinuous current caused by low winding inductance, long vector dwell time, or an unsuitable freewheel path	Capture phase current and switch-node voltage during one complete PWM period
Large ripple despite a stable current command	Applied volt-seconds are too large for the winding inductance	Measure DC-bus voltage, duty ratio, back EMF, and current slope in each switching state
Current feedback becomes noisy after raising the carrier	The ADC sample falls inside a switching transient, the amplifier has not settled, or the shunt is unobservable in that switching state	Plot the ADC trigger against gate commands and compare raw samples at several trigger offsets
Current control becomes unstable although the power stage switches	Loop delay, scaling, sampling, or actuator updates no longer match the configured rates	Log current reference, measured current, regulator output, saturation state, and update timestamps
Heating rises while current ripple falls	Switching, gate-drive, magnetic, and capacitor losses increased faster than ripple-related motor losses decreased	Measure input power and temperatures at equal speed, torque, bus voltage, and cooling conditions

Why does low inductance produce such large current slopes?

Winding current follows di/dt = (v − e − Ri)/L, where v is the applied phase voltage, e is back EMF, R is winding resistance, and L is the effective inductance for the active current path. Switching frequency changes how long each voltage vector acts; it does not change this instantaneous slope.

For the stated 5–10 µH motor and 180–200 V bus target, a bounding calculation using the full bus voltage across the inductance gives:

• 180 V / 10 µH = 18 A/µs
• 200 V / 5 µH = 40 A/µs

These are slope bounds, not predicted ripple. Actual phase voltage depends on topology, modulation vector, duty ratio, back EMF, resistance, commutation state, and the definition of the quoted motor inductance. Calculate ripple from the positive and negative volt-seconds in each state rather than multiplying the full bus voltage by the entire carrier period.

Raising the carrier reduces the time available for current to move during each switching state and can keep conduction continuous. The proposed change from 20–30 kHz to 500 kHz increases switching events by about 16.7 to 25 times. The proposed ±1 A ripple at 500 kHz, compared with ±50 A at a lower rate, is a design target until phase-current measurements confirm it.

Which approach fits a 5–10 µH motor?

Approach	Current-ripple effect	Main cost	Control impact	Decision criterion
Add series inductance	Reduces di/dt directly at the existing carrier rate	Mass, volume, copper loss, core loss, cost, and saturation margin	Changes the electrical plant and normally permits longer PWM periods	Select when a suitably rated inductor meets current, saturation, loss, and packaging limits
Raise PWM toward 500 kHz	Reduces current change per switching state when modulation remains in continuous conduction	Higher switching loss, gate-drive loss, EMI, timing pressure, and thermal loading	Requires synchronized actuation and current sampling; the regulator may run more slowly than the carrier	Select only when the power stage, sensing chain, processor, and thermal design pass measurements at the target voltage and current
Use moderate added inductance and a higher carrier	Shares ripple reduction between magnetic impedance and shorter switching intervals	Retains a smaller magnetic component while reducing the frequency increase	Provides wider sampling windows and lower switching stress than the all-frequency approach	Select when neither a large external inductor nor 500 kHz alone meets loss and packaging limits

For custom hardware, use the hybrid approach as the first design comparison and treat 500 kHz as a measured feasibility target. It provides another degree of freedom when a full-size series inductor would be heavy or saturate, while avoiding an immediate commitment to the maximum proposed carrier rate. An all-frequency solution becomes preferable only if measured total losses, current observability, minimum pulse behavior, and temperature remain acceptable.

Can the current loop run at 20 kHz while PWM runs at 500 kHz?

Yes, the carrier and current-regulator rates can differ. At the proposed values, a 20 kHz regulator executes every 50 µs, and a 500 kHz modulator produces 25 PWM periods during that interval. Hold the regulator output, or a defined modulation command derived from it, between control updates while continuing to generate PWM edges.

Current-loop speed is not determined only by electrical rotational frequency. It also depends on winding inductance and resistance, available voltage, back EMF, desired closed-loop bandwidth, sensor bandwidth, filtering, calculation delay, modulation delay, and actuator saturation. Raising the carrier reduces ripple and can shorten actuation granularity, but a regulator that updates every twenty-fifth carrier cycle still carries its own sampling and computation delay.

If 30k ERPM means 30,000 electrical revolutions per minute, the electrical frequency is 500 Hz. A 20 kHz update rate then provides 40 updates per electrical cycle. That ratio is useful for scheduling but does not prove adequate loop bandwidth or phase margin. Verify the closed-loop response under maximum back EMF and minimum available voltage margin.

Setting	Implementation location	Effect
500 kHz PWM target	Timer period, modulation, gate-driver path	2 µs carrier period and reduced time for transitions and sampling
20 kHz current-loop target	Control scheduler and ADC data path	One regulator update per 25 carrier periods
Deadtime matched to hardware	Complementary-output timer or gate-driver logic	Trades shoot-through margin against deadtime voltage error and waveform distortion
ADC trigger position	PWM-synchronized sampling logic	Places acquisition inside a valid shunt-observation window and outside switching transients

What must change besides frequency and deadtime?

The power stage must complete each transition, settle, and present a measurable current before the next relevant event. GaN switches and high-speed gate drivers can reduce transition time, but layout inductance, gate-loop impedance, common-source inductance, device capacitance, reverse-conduction behavior, and driver propagation matching still set practical limits. Added SiC diodes must be evaluated as part of the actual commutation path rather than assumed to improve every switching state.

Low-ESR and low-ESL ceramic and film capacitance must form a compact high-frequency current loop at the bridge. Bulk capacitance alone cannot supply fast edge current through a high-inductance connection. Measure switch-node overshoot and ringing at the device terminals with probing suited to the edge rate; a distant ground lead can create a misleading waveform.

Low-side shunts simplify some sensing arrangements, but current is not observable through every shunt during every modulation state. At narrow duty ratios, deadtime and switching transients may consume the valid sample window. The amplifier, isolation stage where used, anti-alias filter, ADC acquisition time, and trigger must settle within that window. Firmware also needs a defined response for invalid samples instead of feeding switching spikes into the regulator.

Protection cannot depend solely on a 20 kHz software loop. With calculated current slopes reaching tens of amperes per microsecond under full applied voltage, cycle-scale overcurrent handling belongs in the fast hardware path or an equivalently fast independent mechanism. Set thresholds from the switch, shunt, conductor, and motor limits documented for the finished design.

How should the 500 kHz design be brought up?

1. Confirm the effective phase inductance measurement method and record winding resistance. Determine whether 5–10 µH describes phase-to-phase, per-phase, incremental, or another test configuration.
2. Model each inverter voltage vector with di/dt = (v − e − Ri)/L. Calculate current excursion from vector dwell time at the operating duty ratios; do not use the full bus voltage for the complete PWM period.
3. Calculate losses for the series-inductor, high-frequency, and hybrid approaches. Include switch transitions, conduction, gate drive, capacitors, shunts, added magnetics, and motor ripple-related loss.
4. Configure the PWM timer and verify the actual gate repetition rate with the power stage held in a controlled test condition. Confirm that firmware does not silently clamp or quantize the requested frequency.
5. Set deadtime from measured driver and switch transitions. Check both bridge directions across operating voltage and temperature, then inspect for cross-conduction and deadtime distortion.
6. Synchronize ADC triggering to the PWM. Sweep the trigger point across the available window and identify where the shunt amplifier is settled and the required phase current is observable.
7. Run the current regulator initially with conservative commands. If using 20 kHz control and 500 kHz PWM, confirm exactly 25 carrier periods between regulator updates and define how commands transfer between the two timing domains.
8. Increase bus voltage and current in controlled stages while recording phase current, switch-node voltage, DC-link ripple, regulator saturation, protection events, and component temperatures.

How do you verify that the faster carrier solved the problem?

Compare configurations at the same bus voltage, electrical speed, current command, mechanical load, cooling, and measurement bandwidth. A lower phase-current ripple is not sufficient if total input loss, switch temperature, or measurement error rises beyond the design limits.

Verification item	Pass observation	Failure direction
Continuous phase current	Current no longer collapses to zero where continuous conduction is required	Zero-current intervals remain at relevant operating points
Ripple	Measured peak-to-peak ripple matches the vector-based calculation within measurement and parameter tolerance	Unexpected slopes indicate wrong inductance, voltage assignment, timing, or current scaling
Sampling	Repeated samples taken at the same operating point have no edge-correlated steps	Values change materially when the ADC trigger moves away from a switching edge
Control response	Current tracks commanded steps without sustained oscillation or prolonged saturation	Oscillation, delayed recovery, or duty limiting appears at high back EMF
Power-stage waveform	Deadtime prevents overlap and voltage overshoot remains inside documented component limits	Cross-conduction, excessive ringing, or false protection events occur
Thermal result	All measured temperatures stabilize within the finished design limits	Temperature continues rising or exceeds a documented limit

FAQ