A sequence-control program works by representing the machine as active steps, transition conditions, and actions. This structure gives a learner a repeatable path from process description to ladder logic, while simulation exposes sequencing errors before commissioning.
Step-Transition Mechanism
IEC 61131-3 defines Sequential Function Chart (SFC) for expressing sequential behavior. The term here means a model in which a step records the current process state, a transition specifies when control may move, and an action commands equipment while its associated step is active.
A valid transition requires both the preceding step and its transition condition. When that expression becomes true, the program deactivates the preceding step and activates the next step. This rule prevents a sensor assigned to a later operation from advancing an unrelated part of the sequence.
The main implementation hazard is uncontrolled state overlap. Two ordinary steps active at once can issue conflicting actions; no active step can leave the sequence stalled. Set/reset order can also permit several states to cascade during one PLC scan if later transition logic evaluates newly activated states. Define whether the design permits one or multiple transitions per scan, then structure execution accordingly.
Process-Knowledge Check
Check 1: read the process sequence. Expect a defined initial state, ordered operations, transition conditions, commanded outputs, stop behavior, and restart behavior. Describe the process before selecting instructions because the PLC program acts directly on the machine process.
| Reading | Meaning | Next action |
|---|---|---|
| Every operation has an entry condition and completion condition | The process can be represented as steps and transitions | Proceed to Check 2 |
| An operation depends on an undefined sensor or operator decision | The control requirement is incomplete | Define that condition before programming |
| Automatic, manual, setup, or recovery behavior changes the sequence | The system has multiple operating modes | Create a mode/state matrix, then proceed to Check 2 |
| Safe restart state is unknown | Power-up and interruption behavior cannot be coded deterministically | Obtain the process restart requirement |
Build a program flowchart from the ordered operations. Study the process equipment alongside PLC instructions; instruction knowledge cannot supply missing mechanical, electrical, or operating rules. Use a structured book or training text for the first pass and manufacturer PDF documentation for instruction lookup. Repeated passes should move from overall architecture to instruction details and finally to diagnostic behavior.
Language and Method Check
Check 2: read the engineering software's available languages and instructions. Expect either a native SFC facility or ladder instructions capable of storing step state. S7-Graph provides an SFC language for S7-300/400. The S7-200 does not provide that SFC language, although it has sequence-control relay instructions. Mitsubishi controllers may provide STL instructions; confirm availability in the instruction reference for the selected controller.
| Method | State representation | Primary design concern |
|---|---|---|
| Start/hold/stop circuit | Seal-in logic for each step | Explicitly break the preceding step when advancing |
| Set/reset instructions | Latched step bits | Control set/reset order and prevent unintended overlap |
| STL-like logic | Step-oriented instruction pattern | Keep transition ownership visible |
| Latching relays | Retentive state elements | Define power-cycle and reset behavior |
| Shift register | Active state moved through bit positions | Handle branching, reset, and skipped steps deliberately |
Start/hold/stop, set/reset, and STL-like designs can be mapped across PLC families when equivalent Boolean and state-storage operations exist. Learning one general method deeply is more useful than mixing several patterns in one machine. Set/reset logic is especially direct: each step bit represents an active state, and each accepted transition resets the old state while setting the new one.
Program Architecture Check
Check 3: read the symbol table and program partition. Expect a unique symbolic name and documented purpose for every step bit, transition input, mode command, output command, timer, and internal condition. Then expect a deliberate allocation of logic among the main program, subprograms, and interrupt program.
Use one state owner. Output logic should read step states; it should not independently create hidden sequence states. Keep transition evaluation separate from physical output assignment so a forced output or manual command does not silently advance the automatic sequence.
For multiple operating modes, separate mode selection from sequence state. Define which modes may start or advance the automatic sequence, how manual control interacts with step bits, and which state becomes active after a mode change. A mode/state matrix reveals illegal combinations before ladder entry.
The preferred ordinary sequence is one-hot: exactly one normal step is active. Parallel process branches are an explicit exception and require a documented join condition. If the symbol table shows reused, unnamed, or multiply written state bits, correct the allocation before proceeding to Check 4.
Implementation Procedure
Check 4: trace every transition from the active step to its successor. Expect each transition to test the preceding step, the required process condition, and any applicable mode or permissive condition. A false step condition must block that transition even when its sensor is already true.
- Draw the SFC with the initial step, normal steps, branches, joins, and transition conditions.
- Assign a symbolic state bit to every step and enter all symbols before writing ladder logic.
- Initialize only the defined starting state. Define separately what happens after a normal stop, fault reset, mode change, and power restoration.
- For each transition, combine the active preceding step with its process condition. Add mode or permissive terms only where the process specification requires them.
- On an accepted transition, deactivate the preceding step and activate the successor. Apply one consistent set/reset ordering throughout the program.
- Derive output commands from active steps and required interlocks. Keep output control from writing sequence state.
- Partition repeated equipment logic into subprograms and reserve interrupt logic for functions whose execution requirement actually belongs there.
- Create a simulation of the controlled process with configuration software or a suitable plant model.
SIMITis one stated option for Siemens-oriented simulation.
A documented control-system comparison reduced ladder design and simulated debugging from two weeks with experience-based logic to less than half a day with sequence-control design, followed by a successful first site trial. Treat that result as an example of the method's diagnostic clarity, not as a project-duration estimate.
Simulation and Verification
- Check 5.1: initial-state reading. Expect only the designated initial step active and all transition-dependent commands in their defined initial condition.
- Check 5.2: blocked-transition reading. Activate a future-step sensor while its preceding step is inactive. Expect no state change.
- Check 5.3: accepted-transition reading. Make the current transition true. Expect the preceding step to deactivate, the successor to activate, and the related outputs to follow the new state.
- Check 5.4: state-integrity reading. After every normal transition, expect one ordinary step active unless the chart explicitly defines parallel branches.
- Check 5.5: mode-change reading. Change each supported operating mode at every significant step. Expect the documented hold, reset, or transfer behavior with no unintended automatic advance.
- Check 5.6: interruption reading. Test stop, restart, fault reset, and power-restoration logic in simulation. Expect the state selected by the process restart specification, not whichever latched bit happened to remain active.
- Check 5.7: full-cycle reading. Run nominal and abnormal simulated cycles while monitoring step bits, transition conditions, and outputs. Expect every state change to correspond to one documented transition.
Frequently Asked Questions
Why does a PLC sequence skip more than one step?
Set/reset execution may let a newly activated step satisfy another transition during the same scan. Review instruction order, require the correct preceding-step bit in every transition, and apply the project's defined one-transition-per-scan rule where required.
Why does a sequence have two active steps?
A transition may set the successor without resetting the predecessor, or another routine may write the same state bits. Cross-reference every state-bit write and expect one active ordinary step unless the SFC defines a parallel branch.
Why does manual mode disturb the automatic sequence?
Manual output commands and automatic state changes have probably been coupled. Separate mode selection, sequence state, and output assignment; then define whether a mode change holds, resets, or transfers the active step.
How do I know a PLC sequence is ready for commissioning?
Complete the final verification step: run nominal and abnormal simulated cycles while trending step bits, transition conditions, and outputs, and expect every state change to match one documented transition.