IM 151-7 CPU Not Accessible: MPI Reset and MMC Configuration

The SIMATIC ET 200S IM 151-7 CPU is an interface module that combines a Profibus DP slave connection with an integrated S7-300-class CPU, used to add local intelligence to an ET 200S station. When a programmed Micro Memory Card (MMC) is inserted, the IM 151-7 CPU no longer powers up as a default MPI node and can become invisible to STEP 7 "Accessible Nodes" scans, even though the power LED is on and the STOP LED is blinking. This article walks through the diagnostic logic, the MRES overall-reset sequence, PG/PC interface configuration, and the integration path to a master CPU 313C.

1. Problem Description

Reported symptoms on a bench-top IM 151-7 CPU (typical order numbers 6ES7151-7AA20-0AB0 or 6ES7151-7AB00-0AB0):

• PG/PC connected to the IM 151-7 CPU through the MPI/DP port using a Siemens PC adapter (PC Adapter USB, CP 5512, CP 5611, or compatible).
• STEP 7 (SIMATIC Manager or TIA Portal) "Accessible Nodes" returns an empty list.
• Removing the MMC restores detection: the CPU then appears as MPI=2 Direct at 187.5 kbit/s.
• With the MMC inserted, the POWER LED is on and the STOP LED blinks at approximately 0.5 Hz (a slow, even blink).
• Swapping the MMC has no effect; the new card also blocks MPI access.
• The CPU must be commissioned so it can later be linked to a master S7-300 CPU 313C.

2. Root Cause Analysis

Per the SIMATIC ET 200S IM 151-7 CPU Interface Module manual, an IM 151-7 CPU that is powered up without an MMC defaults to an MPI interface with:

• Default MPI address: 2
• Highest Station Address (HSA): 31
• Default baud rate: 187.5 kbit/s
• Default I-slave functionality: not enabled

When an MMC is inserted, the CPU reads its operating mode, MPI/DP configuration, and project data from the card. If the project stored on the MMC contains an HW Config that has reconfigured the X2 MPI/DP port as a Profibus DP slave interface, the CPU boots with a Profibus DP node address and a Profibus baud rate. STEP 7's MPI "Accessible Nodes" scan cannot find a Profibus slave — only MPI masters respond to the MPI poll — so the node appears invisible.

The blinking STOP LED confirms the CPU is in the "STOP caused by missing or invalid MMC project" state. The CPU is not faulty; the port type stored on the card simply does not match the access path the programmer is using.

2.1 Other Possible Root Causes

3. Diagnostic LED Patterns on the IM 151-7 CPU

The IM 151-7 CPU front panel has four status LEDs (POWER, STOP, RUN, and the SF/ACCESS combination on later variants). Reading them before any reset prevents you from clearing useful state.

4. Overall Reset (MRES) Procedure

The IM 151-7 CPU borrows the S7-300 MRES sequence. The reset clears the work memory, places the CPU in STOP, and — if the mode selector is then held in MRES during a power cycle — formats a fresh project slot. This is the only safe way to recover an MMC that contains a project re-mapping the X2 port to Profibus DP.

4.1 STEP 7 Classic — MRES Sequence

1. Set the mode selector to STOP. The STOP LED is on (or blinking, if the CPU is requesting a reset).
2. Hold the mode selector in the MRES position for at least 3 seconds, then release. The STOP LED should change pattern, indicating the CPU has registered the request.
3. Within 3 seconds, turn the selector back to MRES and hold it again. The STOP LED will flash briefly and then go to a steady ON, confirming the overall reset.
4. Release the selector back to STOP. The CPU is now reset; the work memory is empty; the port type reverts to the firmware default (MPI, address 2).
5. If the STOP LED continues to blink, the reset was not accepted. Repeat the sequence; on the third failure, suspect the MMC (replace it — see §5).

4.2 TIA Portal Equivalent

TIA Portal exposes the same action under Online & Diagnostics → Functions → Reset to factory settings. The "Format PLC" / "Reset memory" options correspond to the MRES behaviour. Use the Online & Diagnostics view, select the IM 151-7 CPU as the online target (it will only be visible if the access path already works), and trigger Reset memory. After the reset, the CPU is back to MPI=2.

4.3 Emergency IP Address Fallback (Reference)

For S7-1200/1500 CPUs, Siemens documents an emergency (temporary) IP address to recover from a network outage. The IM 151-7 CPU does not have an IP-based interface — its only programming port is the MPI/DP physical connector — so this mechanism does not apply. If MPI is unreachable, the MRES procedure is the recovery path.

5. MMC Requirements and Approved Types

Only Siemens-branded MMCs are supported. Third-party SD/MMC cards almost always fail the integrity check and produce a continuous blinking STOP LED.

6. PG/PC Interface Configuration

After the MRES reset, configure the programming interface to talk MPI at 187.5 kbit/s to the default address 2.

6.1 STEP 7 V5.x (SIMATIC Manager)

1. Open Start → SIMATIC → STEP 7 → Set PG/PC Interface.
2. Select the access point: S7ONLINE (STEP 7) → PC Adapter (Auto).
3. Click Properties:
   • Tab MPI: Transmission rate 187.5 kbps, Highest station address 31, profile MPI.
   • Tab Profibus: Leave as default unless the adapter supports both — set the bus parameters only if STEP 7 reports a bus profile mismatch.
4. Click Diagnostics → Test. The PG/PC interface test should report "OK" against the IM 151-7 CPU at MPI address 2.
5. In the SIMATIC Manager, choose PLC → Accessible Nodes. The IM 151-7 CPU should appear with its MPI address, firmware version, and order number.

6.2 TIA Portal

1. Online → Accessible devices or Project → Devices & networks → Add device → Accessible device.
2. Set the PG/PC interface type to PC Adapter and the protocol to MPI.
3. Set transmission rate 187.5 kbps, HSA 31.
4. Run Show accessible devices. The IM 151-7 CPU is identified by its order number (6ES7151-7...) and its integrated CPU firmware version (visible in the device list).

7. Reading and Rewriting the Project on the MMC

Once "Accessible Nodes" lists the IM 151-7 CPU, do not stop at the read-back. The project on the card is what caused the original symptom. Open PLC → Upload to PG/PG (STEP 7 V5) or Online → Upload from device (TIA) to recover the project, then verify or correct the port type.

7.1 Check the Port Assignment in HW Config

1. Open the IM 151-7 CPU in HW Config.
2. Select the X2 (MPI/DP) interface.
3. Confirm the Interface dropdown: it must read MPI. If it reads Profibus DP slave, the MMC project is the cause of the access loss.
4. Set the Address to a free MPI address (default 2; on a multi-MPI bus, use a value between 3 and 30).
5. Save and compile, then download back to the CPU/MMC.

7.2 Re-Commissioning Workflow

1. MRES (§4) to clear work memory.
2. PG/PC interface set to MPI 187.5 kbps (§6).
3. Upload the existing project to recover the S7 program and HW Config.
4. Edit HW Config so X2 = MPI, address = 2 (or another free address).
5. Download the corrected project to the IM 151-7 CPU.
6. Verify "Accessible Nodes" still shows the CPU with the new address.
7. Mark the MMC with the project name and the date to prevent recurrence.

8. Integrating the IM 151-7 CPU with a Master CPU 313C

The CPU 313C (order number 6ES7313-5BF03-0AB0) has a single integrated MPI/DP port that operates as MPI only out of the box. It does not support Profibus DP master functionality without an expansion. This constraint dictates the choice of integration path.

8.1 Integration Path Matrix

8.2 Recommended Path: MPI with S7 Communication

For most users who only have a stock CPU 313C (no DP, no CP 342-5), the simplest link is MPI-to-MPI using S7 communication function blocks. This is the path implied by the original help request ("connect this CPU to main 313C CPU") and it does not require any hardware upgrade.

Configuration in HW Config of the Master (313C)

1. Open the S7 project for the CPU 313C.
2. In the master HW Config, the 313C's X1 (MPI/DP) must be set to MPI with the master MPI address (typically 2).
3. Add a new MPI node: Insert → Station → SIMATIC 300 Station for the IM 151-7 CPU or use Insert → Partner → MPI if the IM 151-7's project is standalone.
4. Set the partner MPI address to match the IM 151-7 CPU (4 by default if you have moved it off 2).
5. Save and compile the master project.

Communication Block Pattern (STEP 7 Classic, STL)

// Master call: read 10 bytes from IM 151-7 CPU DB100 starting at byte 0
CALL "X_GET" , DB103      // SFC 7, instance DB auto-generated
  REQ       := TRUE       // Rising edge starts the job
  CONT      := TRUE       // Keep the connection
  DEST_ADDR := W#16#4     // MPI address 4 (= IM 151-7 CPU)
  REMOTE_VAR:="DB100.AREA"// ANY pointer to remote DB100.DBX0.0 BYTE 10
  BUSY       :=X_WORK
  RD         :=X_DONE

Where REMOTE_VAR is an ANY pointer built in the usual form:

// Build ANY: DB 100, area DB, byte 0, bit 0, length 10
P#DB100.DBX0.0 BYTE 10

For cyclic bidirectional data, pair the read with SFC 8 ("X_PUT") and trigger it from a 100 ms OB1 cycle flag.

Verifying the Link

1. Both CPUs in RUN (RUN LEDs on, no SF/BUSF).
2. Open the master project online: PLC → Accessible Nodes lists the IM 151-7 CPU at the configured MPI address.
3. Open the master diagnostic buffer: there should be no communication errors and the SFC 7/8 instance DB should show BUSY = 0, DONE = 1.
4. Force a known pattern into IM 151-7 DB100.DBX0.0 from its online project; the same bytes appear in the master's receive area.

9. Verification Matrix

10. Troubleshooting Matrix — Persistent Failure

If the IM 151-7 CPU remains unreachable after the procedure above, work through this matrix before declaring hardware failure.

11. Field-Proven Caveats

• Pulling the MMC is not a fix. It exposes the firmware default, but as soon as the MMC is reinserted the project reloads and the problem returns. The project itself has to be edited.
• CP 5512 is MPI+Profibus. If the IM 151-7 CPU has been reconfigured to Profibus, scanning with the CP 5512 set to Profibus is the only way to find it. Scanning only MPI will fail.
• HSA must match. If the IM 151-7 CPU's project has been edited to HSA = 15, the PG/PC interface must also be set to HSA = 15, otherwise "Accessible Nodes" can return false negatives.
• Passwords survive MRES. Know-how-protected blocks stay protected after a memory reset. The CPU remains accessible (project loads), but the protected blocks are unreadable.
• Firmware version matters. An MMC written by a CPU 314C-2 DP with firmware V3.x may not boot in an IM 151-7 CPU with firmware V2.x. Use the correct firmware line for the card, or reflash the CPU before inserting the card.
• Power supply to the ET 200S rack. A weak 24 V supply can cause the IM 151-7 CPU to behave as if the MMC were missing (intermittent boot). Verify ≥ 22 V at the power module terminals with the station under load.
• Backplane and terminal modules. A missing or mis-seated terminal module downstream of the IM 151-7 CPU causes group-error SF LED, not a STOP blink. If SF is on in addition to STOP blinking, re-seat the I/O modules first.

12. Summary Workflow

1. Observe LEDs — POWER on, STOP blinking confirms the CPU wants a reset.
2. Set PG/PC interface to PC Adapter (MPI) at 187.5 kbps, HSA 31.
3. MRES the IM 151-7 CPU with the MMC inserted.
4. Re-open Accessible Nodes; the CPU should appear at MPI=2.
5. Upload the project, verify X2 = MPI, save, download back to the CPU.
6. Configure the master CPU 313C's MPI/DP port as MPI.
7. Use SFC 7 (X_GET) / SFC 8 (X_PUT) for cross-CPU data exchange; or migrate to a Profibus DP master (CPU 313C-2 DP or CP 342-5) if higher throughput is required.