Implementing Night Period Time Logic on ET200S IM 151-8 PN/DP

1. Problem Definition: Triggering a Boolean Across the Midnight Boundary

The functional requirement is the canonical irrigation/water-conservation pattern that comes up on most greenfield ET200S sites: a single TRUE/FALSE tag must be TRUE for every second between 21:00:00 and 06:59:59 local time, and FALSE outside that band, with the boolean driving a low-flow valve so that the night-period trickle does not overlap the daytime high-consumption cycle. The interval crosses midnight, which makes the trivial ladder formulation (hour ≥ 21 AND hour ≤ 7) wrong: that AND evaluates false across midnight. The correct reading is hour ≥ 21 OR hour < 7, and the comparison itself must be derived from the PLC's wall-clock rather than any user-entered shift table.

The platform is the ET200S IM 151-8 PN/DP (catalog 6ES7151-8AB01-0AB0, firmware V3.x) programmed in TIA Portal V15.1 (Update 4) using LAD. With those constraints fixed, the question is which instruction set to use and which library blocks are guaranteed to compile.

2. Why the LGF Library LGF_TimerSwitch Does Not Compile on ET200S

The first instinct on TIA Portal V15.1 is to drop in LGF_TimerSwitch from the Siemens LGF Library. The block compiles cleanly on an S7-1500 target and immediately returns the desired boolean. On ET200S IM 151-8 PN/DP, however, the same block produces:

Compile error: Data type DTL not supported by the CPU
Block LGF_TimerSwitch cannot be used in this device family

The reason is structural, not a version mismatch.

Per the official LGF Library Manual (Siemens Support Entry 109479728), every block in the LGF library targets the SIMATIC S7-1200 (firmware V4.2 and above), the SIMATIC S7-1500 (firmware V2.0 and above), and the S7-PLCSIM simulator (V14 and above). ET200S IM 151-8 PN/DP, despite carrying its own CPU, executes the S7-300 instruction set and so cannot declare DTL tags, cannot perform ULInt arithmetic, and cannot load the LGF library. Upgrading TIA Portal to Update 4 does not relax the type coverage of the CPU class.

3. ET200S IM 151-8 PN/DP Hardware and Software Constraints

The practical consequence is that any object uses the S7-300 instruction subset: SFC and SFB calls, BCD byte slicing, and classic comparator/accumulator ladder. Anything that builds on the advanced bit/byte types of S7-1500 has to be ported to S7-300 primitives by hand.

4. Solution Overview: Three Engineering Paths

Three deterministic approaches solve the same problem on ET200S, in increasing order of code reuse and decreasing order of bespoke development.

5. Path 1: FC20 / TimeDB From Siemens FAQ 43566349

5.1 Download and import

The Siemens support FAQ 43566349 provides a ST/LAD source bundle containing two artefacts:

• FC20 — a comparator FB that accepts a current DATE_AND_TIME input and produces a boolean output that latches between configurable turn-on and turn-off timestamps.
• TimeDB — an instance DB holding all parameter tunables (on time, off time, enable, status).

Both blocks were written before DTL existed and therefore operate exclusively on the 8-byte DATE_AND_TIME BCD layout, which makes them drop-in compatible with ET200S.

5.2 Wire-up

// Pre-conditions in TIA Portal V15.1
// - Add the FC20 and TimeDB blocks to the project tree
// - Open TimeDB and set:
//     TimeDB.OnHour   := 21
//     TimeDB.OnMinute := 0
//     TimeDB.OffHour  := 7
//     TimeDB.OffMinute:= 0

// Network 1 — Read wall clock
CALL "READ_CLK"                 // SFC1
   RET_VAL := MW100
   CDT     := "myDB".runtime    // DATE_AND_TIME (8 bytes)

// Network 2 — Invoke the timer comparator
CALL FC20
   currentDT  := "myDB".runtime
   timeParams := "TimeDB"
   out        := "myDB".night_period_active

With OnHour = 21 and OffHour = 7, FC20 produces TRUE from 21:00 through 06:59, exactly matching the requirement. The FAQ source places the comparison in TIME_OF_DAY (TOD, unsigned milliseconds since 00:00) arithmetic; this internalises the midnight-crossing logic into the supplied FC and avoids ladder overload.

6. Path 2: Native LAD Logic Using SFC1 READ_CLK

This path keeps the implementation entirely inside TIA Portal’s standard S7-300 instruction set and avoids external libraries. It is the option most field engineers pick on first contact with ET200S and is the easiest to defend during a code review.

6.1 DB declaration (TIA Portal V15.1 LAD)

DATA_BLOCK "myDB"   // global DB, retainable attributes can be set per element
  STRUCT
    runtime      : DATE_AND_TIME;    // 8 bytes BCD, populated by SFC1
    hour         : INT;             // 0..23, mirror of .HOUR element
    minute       : INT;             // 0..59
    second       : INT;             // 0..59
    ret_val      : INT;             // SFC1 status, retain last error
    night_high   : BOOL;            // hour >= 21 latch
    night_low    : BOOL;            // hour < 7 latch
    night_active : BOOL;            // final driver to the valve
  END_STRUCT;
END_DATA_BLOCK

6.2 Network 1 — Read wall clock

CALL "READ_CLK"                          // SFC1
   RET_VAL := "myDB".ret_val
   CDT     := "myDB".runtime

6.3 Network 2 — Mirror HOUR and clear latches each cycle

      L     "myDB".runtime.HOUR           // implicit INT element access
      T     "myDB".hour                   // local INT mirror
      L     "myDB".runtime.MINUTE
      T     "myDB".minute
      L     "myDB".runtime.SECOND
      T     "myDB".second

      CLR                                     // reset latches (avoid sticky ON
      =     "myDB".night_high                 //  if the previous cycle went RUN
      =     "myDB".night_low                  //  without an updated SFC1 read)

6.4 Network 3 — Hour ≥ 21

      L     "myDB".hour
      L     21
      >=I
      S     "myDB".night_high

6.5 Network 4 — Hour < 7

      L     "myDB".hour
      L     7
      <I
      S     "myDB".night_low

6.6 Network 5 — Combine and drive the valve

      O     "myDB".night_high
      O     "myDB".night_low
      =     "myDB".night_active
      =     %Q0.0                          // example mapping to the valve output

6.7 SCL variant for cleaner review

"myDB".ret_val := READ_CLK(CDT := "myDB".runtime);
"myDB".hour    := "myDB".runtime.HOUR;

IF ("myDB".hour >= 21) OR ("myDB".hour < 7) THEN
    "myDB".night_active := TRUE;
ELSE
    "myDB".night_active := FALSE;
END_IF;

This code does not depend on DTL, ULInt, or any S7-1500 class type, so it compiles on every ET200S IM 151-8 PN/DP firmware revision 1.x through 3.x. The SFC1 call runs in roughly 35–60µs per scan on an IM 151-8 firmware V3.x CPU, and element access via .HOUR is fully supported on TIA Portal V15.1 against a S7-300 instruction target.

7. Path 3: Porting LGF_TimerSwitch From S7-1500 to ET200S

7.1 Create a temporary S7-1500 project

The LGF library blocks are verified only on S7-1200/1500, so opening the block source on a stub S7-1500 project preserves the original test assertions and gives the compiler target to validate the port.

7.2 Replacement map

7.3 Convert element access

Where the original LGF block reads DTL fields such as inputTime.HOUR, the ported version simply substitutes a DATE_AND_TIME variable with the same named fields. The element metadata is identical because both DTL and DATE_AND_TIME encode HOUR/MINUTE/SECOND as BCD values accessible by symbolic name.

7.4 Replace ULInt / LInt arithmetic

The critical arithmetic block in LGF_TimerSwitch subtracts two timestamps to compute an unsigned millisecond offset. With ULInt, the wraparound semantics are intentional; switching to UDInt reproduces the same behaviour as long as the inputs stay in 0..86 399 999. Use a guard line to clamp the inputs before subtraction:

IF i_switchTime < 0 THEN i_switchTime := 0; END_IF;
IF i_switchTime > 86399999 THEN i_switchTime := 86399999; END_IF;

Compile the ported source in the S7-1500 stub project first to verify logic equivalence, then download the same FC and DB to the ET200S IM 151-8 PN/DP target.

8. Handling the Midnight-Boundary Edge Cases

8.1 Inclusive vs exclusive endpoints

The interval 21:00–07:00 has multiple interpretations. The most common convention in irrigation control is exclusive of the end, i.e., TRUE from 21:00:00 through 06:59:59 and FALSE from 07:00:00. If the END should be inclusive, the comparison becomes hour ≥ 21 OR (hour ≥ 0 AND hour ≤ 7), which simplifies to the same logic at hour granularity but diverges for minute-second resolutions where the boundary at 07:00:00 must be captured. Validate which convention the process needs before writing the ladder; the wrong default at one second boundary can cost a litre of water per night per valve.

8.2 Daylight saving and NTP drift

If the PLC receives NTP via PROFINET (CP), the wall clock jumps by one hour at the DST transition. The boolean does not glitch because the comparison runs every scan and the transition takes effect immediately. The watch item to validate is the date display in HMI: .DATE element will roll over at midnight regardless. If the site has no NTP source, the IM 151-8 PN/DP RTC drifts about ±1–2 ppm per month, so the latch can shift by minutes per year; ladder should be reviewed annually.

8.3 PLC mode transitions

After STOP→RUN, the runtime DB element .runtime retains its previous value until the first SFC1 call returns. To avoid a 24-hour stale output during restart, place SFC1 READ_CLK in OB1 (or OB35 cyclic interrupt at 1 s) without conditional gate. ET200S IM 151-8 PN/DP firmware V3.x calls SFC1 reliably even after a full power-cycle, but the first read after STOP→RUN can arrive up to one OB1 cycle late if SFC1 is parked in a slow-priority execution level.

9. Step-by-Step Commissioning Checklist

1. Open the TIA Portal V15.1 project that contains the ET200S station with IM 151-8 PN/DP as head module.
2. Confirm the device configuration online via "Online & Diagnostics → Module Information" and record the catalog number and firmware revision.
3. Add a global DB (e.g., myDB) with the structure from §6.1 if Path 2 is used.
4. If Path 1 is used, import the FC20 / TimeDB bundle from FAQ 43566349 as external sources and recompile inside the project.
5. Insert the SFC1 READ_CLK call as the first network of OB1 (Path 2) or as the clock provider (Path 1).
6. Wire the final boolean (night_active) to the valve output word; for a fail-safe valve, route through the assigned F-channel rather than direct %Q.
7. Set the on-board time using "Online & Diagnostics → Set Time" or via SFC0 if the cabinet has no NTP.
8. Force the runtime HOUR element to 21 via the watch table; verify the boolean asserts within one scan.
9. Force the runtime HOUR element to 6; verify boolean is TRUE.
10. Force the runtime HOUR element to 7; verify boolean releases.
11. Force the runtime HOUR element to 23:59 and step the clock by 1 minute at a time using SFC0; verify the latch turns ON at exactly 21:00 local time.
12. Observe the boolean for at least 24 hours of real wall-clock transitions before releasing to operations.

10. Verification and Acceptance Test

10.1 Simulation with PLCSIM

S7-PLCSIM V15 supports the IM 151-8 PN/DP station type since V15.0. Use a 24-hour accelerated simulation by calling SFC0 in OB35 every 100 ms with a clock that advances 1 min per execution. Log the boolean transition points to a trace and confirm 21:00:00 and 07:00:00 transitions occur on the expected scan.

10.2 Field test with SFC0 SET_CLK

For acceptance on the live CPU, an alternative is to temporarily set the system time to 20:59:50 and let the clock run to 21:00:00 naturally. Use an HMI tag or watch table that increments the timestamp by 1 minute every 60 seconds and log the boolean change; this generates an audit trail for regulatory or quality audits.

10.3 Long-duration trace

Many facilities run the logic for 7–30 days before sign-off. Place a trace on night_active with a 1 s sample rate and a 30-day buffer (~2.6 MB of trace data). Confirm zero unexpected transitions, in particular during DST crossover (where applicable) and during power outages.

11. Troubleshooting Matrix

12. Performance, Scan-Time, and Memory Footprint

For an irrigation application, the OB1 cycle budget for an ET200S IM 151-8 PN/DP is typically 5 ms or more, so 50–120µs of interval-detection logic is well below 3% of the cycle and does not require acceleration to a higher-priority OB.