Implementing SHRB Bit Shift Register on S7-1200 and S7-1500

Overview: Why FC 92 (SHRB) Cannot Be Loaded Directly into S7-1200/1500

The classic SIMATIC S7-300/S7-400 FC 92 SHRB (Shift Right Bit) belongs to the legacy "Standard Library – Bit Logic Functions" that ships with STEP 7 V5.x. When you open a STEP 7 V5 project that contains FC 92 in TIA Portal and try to migrate it into an S7-1200 or S7-1500 CPU, the migration tool reports that the block is not supported on the target. The instruction set of the S7-1200/1500 firmware family is binary-compatible only with the TIA Portal instruction catalog, not with the V5.x standard library. Consequently, the FC must be replaced by a functionally equivalent TIA Portal instruction or by a user-written FC/FB that performs the same single-bit shift operation.

This reference shows exactly how to reproduce the FC 92 behaviour on S7-1200 (firmware V4.0 and higher) and S7-1500 (firmware V1.0 and higher) using native TIA Portal instructions, and how to encapsulate the logic in a reusable FC so that the call interface matches the legacy block.

Prerequisites

• TIA Portal V16, V17 or V18 with installed SIMATIC S7-1200/S7-1500 support package. TIA Portal V19 is supported for S7-1200 (firmware V4.5+) and S7-1500 (firmware V2.9+).
• S7-1200 CPU with firmware V4.2 or later (CPU 1211C, 1212C, 1214C, 1215C, 1217C). Firmware V4.0 is the minimum for the SHR/SHL/ROL/ROR instructions used in this article.
• S7-1500 CPU with firmware V1.8 or later (CPU 1511, 1513, 1515, 1516, 1517, 1518). Bit-shift instructions require firmware V1.0 as a minimum, but later firmware adds the BYTE/WORD/DWORD/LWORD variants.
• Programming language: LAD, FBD, or SCL. STL is available only on S7-1500.
• Access to the TIA Portal Online Help – Function (FC) and the S7-1200/S7-1500 system manuals referenced at the bottom of this article.

FC 92 (SHRB) Behaviour on S7-300/S7-400

FC 92 SHRB is a single-bit shift register. The formal parameters are:

On every rising edge of CLK the contents of the bit array starting at S_BIT are shifted toward the high-order bit by one position; S_DATA is written into the low-order bit. Bits shifted past the high boundary are discarded. The block writes back to absolute or symbolic addresses pointed to by S_BIT.

Why the Block Does Not Migrate

The S7-1200/1500 instruction set drops several legacy V5.x features:

• Memory-area pointers (P#M0.0, P#DB1.DBX0.0) used by the POINTER data type are not accepted as formal parameters on S7-1200/1500 FCs. The CPU only resolves symbolic or fully-qualified absolute addresses during compilation.
• The "old" ANY pointer (16-byte legacy header) used by older V5.x variants of FC 92 is not part of the TIA Portal type system. TIA Portal ANY pointers have a different internal layout and are restricted in how they can be passed to instructions.
• The standard library that ships with STEP 7 V5.5 SPx is a separate CD image and is not installed with TIA Portal. The library must be removed before migration; only the user-written code is migrated.

As a result, the only supported approach is to reimplement the behaviour using the native bit-shift instructions documented in the TIA Portal information system.

Native Bit-Shift Instructions on S7-1200/1500

TIA Portal exposes the following bit-shifting instructions under Instructions > Bit logic operations and Instructions > Move operations:

All four instructions are available on S7-1200 firmware V4.0+ and on every S7-1500 firmware. LWORD variant requires S7-1500 firmware V2.0+ and S7-1200 firmware V4.2+.

Reimplementing SHRB as a User-Written FC in TIA Portal

The cleanest replacement is a single-input/single-output FC that hides the data-type juggling from the caller. The following SCL snippet creates a parameter set that mirrors the legacy FC 92 interface as closely as TIA Portal will allow.

FC block interface

SCL implementation

FUNCTION "FC_SHRB" : Int
{ S7_Optimized_Access := 'TRUE' }
VERSION : 0.1
   VAR_INPUT
      S_DATA  : Bool;   // Bit shifted in at position 0
      CLK     : Bool;   // Shift clock
      BIT_COUNT : Int;  // 1..32 valid bits in SHIFT_WORD
   END_VAR
   VAR_IN_OUT
      SHIFT_WORD : DWord; // Bit array, LSB = newest
   END_VAR
   VAR_OUTPUT
      RET_VAL : Int;
   END_VAR
   VAR
      CLK_EDGE : Bool;   // Edge memory
   END_VAR
BEGIN
   RET_VAL := 0;
   IF (BIT_COUNT < 1) OR (BIT_COUNT > 32) THEN
      RET_VAL := 1;                            // Range error
      RETURN;
   END_IF;

   IF CLK AND NOT CLK_EDGE THEN                // Rising edge
      // 1. Shift everything left by one to make room for the new bit
      SHIFT_WORD := SHL(SHIFT_WORD, 1) OR DINT_TO_DWORD(BIT_COUNT - 1);
      // 2. Clear bits above BIT_COUNT (one-shots)
      SHIFT_WORD := SHIFT_WORD AND
                    SHL(DWORD#1, BIT_COUNT) - DWORD#1;
      // 3. Insert the new bit at position 0
      IF S_DATA THEN
         SHIFT_WORD := SHIFT_WORD OR DWORD#1;
      END_IF;
   END_IF;

   CLK_EDGE := CLK;
END_FUNCTION

LAD/FBD Alternative Without Writing Code

If you prefer to stay inside the instruction palette, the SHRB behaviour can be reproduced in two network segments:

1. Network 1 — edge detection: Place a P= (scan operand for positive edge) coil driving a tag shrb_clk_one. Use a second tag shrb_clk_memento as the edge memory if you cannot use the implicit edge bit of the FC.
2. Network 2 — shift and OR: Place an SHL instruction with IN = SHIFT_WORD, N = 1, OUT = SHIFT_WORD. Then place a parallel branch with OR that conditionally ORs the constant 1 into bit 0 of SHIFT_WORD when S_DATA is TRUE.
3. Network 3 — mask: AND SHIFT_WORD with the constant mask SHL(1, BIT_COUNT) - 1 to keep only the requested number of bits.

The three networks can be wrapped in a single FC by selecting Insert > FC and pasting them. The FC will then be called from the OB1 (or cyclic OB) just like the legacy FC 92.

Migrating a STEP 7 V5 Project that Uses FC 92

1. Open the STEP 7 V5 project in TIA Portal via Project > Migrate project. TIA Portal will warn that unsupported library blocks must be removed.
2. Delete every instance of the legacy FC 92 SHRB from the program blocks. Make a list of each call site and the absolute pointer passed in S_BIT.
3. Add a new FC to the S7-1200/1500 program. Paste the SCL code above (or the LAD networks) and compile. Address compiler warnings about implicit type conversions before downloading.
4. For each call site, replace the old pointer argument with a DWord tag that has been mapped to the original memory area. For example, the bits M0.0 to M3.7 map to "ShiftWordM0" of type DWORD in a global DB. The four bytes must be unique – they cannot overlap with other symbolic tags used by the rest of the program.
5. Wire the call: S_DATA = digital input; CLK = cycle bit or pulse generator; BIT_COUNT = constant or configurable tag; SHIFT_WORD = DWord tag.

Verification and Commissioning

Use the following checks before going online to the real CPU:

Troubleshooting Matrix

Reference: Officially Available Bit-Shift Instructions in TIA Portal

The complete list of bit-shifting instructions available on the S7-1200/1500 is found in the TIA Portal information system under Instructions > Bit logic operations. Below is a compact mapping back to the STEP 7 V5 standard library.

For the canonical instruction catalogue, consult the S7-1200 and S7-1500 system manuals linked below.