Interpreting S7-300 STL Networks with Multiple OR Logic Steps

Overview: Why One STL Network Holds Several Logic Steps

In Siemens SIMATIC S7-300 programming with STEP 7 (TIA Portal or the legacy SIMATIC Manager), STL (Statement List / STL stands for "STeuerungs-Listen-Programmierung) lets a single network contain more than one independent logic step. This is one of the few structural freedoms STL keeps that LAD (Ladder / Ladder Diagram) and FBD (Function Block Diagram) cannot mirror directly. The example below shows eight boolean inputs being combined to drive four outputs inside a single Function (FC) network:

O   #IN0
O   #IN4
=   #OUT5
O   #IN1
O   #IN4
=   #OUT6
O   #IN2
O   #IN4
=   #OUT7
O   #IN3
O   #IN4
=   #OUT8

Each pair of lines beginning with O (OR) followed by a line beginning with = (assign) is a self-contained logic step. The four steps share no signals with each other except for the common operand #IN4, which is re-read by the PLC on every CPU scan where the FC is called.

STL Fundamentals: Operands, Operators, and the Logic Step

A logic step in STL is one or more check statements that load and combine boolean operands into ACCU1, terminated by exactly one conditional statement (assign, set, reset, jump). The step ends as soon as the assignment executes and ACCU1 is then re-used by the next step in the same network.

Prerequisites for Reading and Converting the Example

1. STEP 7 V5.5 SP4 (or later) or TIA Portal V16 (or later) installed with the S7-300 HSP (Hardware Support Package) loaded so that the CPU type is recognized.
2. The project open in SIMATIC Manager or TIA Portal with the FC containing the snippet visible in the STL editor.
3. The FC interface declarations known so that #IN0 ... #IN3, #IN4, and #OUT5 ... #OUT8 can be mapped to their absolute addresses (for example, IB0 and QB0).
4. The FC's call site located (OB1, OB35, or another block) so you can verify what data is wired into the formal parameters at runtime.

Step-by-Step Interpretation of the Sample Network

Using the operand table below as a translation key, the snippet maps to four independent boolean equations that share a common enable signal #IN4.

Logic Step 1 (lines 1 to 3)

O   #IN0
O   #IN4
=   #OUT5

Boolean equation: #OUT5 := #IN0 OR #IN4. ACCU1 is first OR'd with #IN0, then OR'd with #IN4; the resulting 1-bit value is written to #OUT5.

Logic Step 2 (lines 4 to 6)

O   #IN1
O   #IN4
=   #OUT6

Boolean equation: #OUT6 := #IN1 OR #IN4. ACCU1 is overwritten by the new chain; previous #OUT5 value is preserved because the assignment already copied ACCU1 to that output bit.

Logic Step 3 (lines 7 to 9)

O   #IN2
O   #IN4
=   #OUT7

Boolean equation: #OUT7 := #IN2 OR #IN4.

Logic Step 4 (lines 10 to 12)

O   #IN3
O   #IN4
=   #OUT8

Boolean equation: #OUT8 := #IN3 OR #IN4.

The full set of equations is therefore:

#OUT5 := #IN0 OR #IN4
#OUT6 := #IN1 OR #IN4
#OUT7 := #IN2 OR #IN4
#OUT8 := #IN3 OR #IN4

Signal #IN4 acts as a global enable: whenever #IN4 = 1, all four outputs follow their respective #INx. If you prefer the conceptual model of an enable/disable switch, the equivalent structured text form is:

IF #IN4 THEN
    #OUT5 := #IN0;
    #OUT6 := #IN1;
    #OUT7 := #IN2;
    #OUT8 := #IN3;
ELSE
    #OUT5 := 0;
    #OUT6 := 0;
    #OUT7 := 0;
    #OUT8 := 0;
END_IF;

Why LAD and FBD Cannot Auto-Convert This STL

Siemens documents this restriction in the official STEP 7 online help (entry ID 21952992):

• In LAD, a network may contain only one current path between the left and right power rails. Two independent parallel branches sharing no contacts cannot co-exist in a single rung.
• In FBD, every assignment must be the only output of its enclosing box. Putting four & (OR) boxes followed by four = assignments in a single network violates the IEC 61131-3 graphical placement rules that STEP 7 enforces for FBD display.
• STL has no such graphical constraint; the accumulator is a free resource that can be reused once the previous step's result has been committed with =.

Manual Conversion Procedure: STL to LAD or FBD

1. Right-click the network title bar and select Insert Network above the current one until you have four empty networks.
2. Cut the lines for step 1 (O #IN0 / O #IN4 / = #OUT5) and paste them into network 1.
3. Repeat for steps 2, 3, and 4 in networks 2, 3, and 4.
4. Switch the FC's editor language to LAD or FBD via Options > Editor Language or the block properties dialog.
5. Compile; STEP 7 will now display each step as its own rung (LAD) or function block (FBD).
6. Watch for warnings in the "Go to Location" panel; jump-instructions, accumulator word operations, and indirect addressing are the typical remaining reasons a network refuses conversion.

Resulting LAD (Network 1 example)

       |    #IN0      #IN4
-------| |-----------| |---( #OUT5 )---

Resulting FBD (Network 1 example)

#IN0 --+OR+-- #OUT5
#IN4 --+   +

Field-Proven Caveats When Refactoring This Pattern

• Watch the scan order. Because each = is committed immediately, later steps cannot react to earlier outputs within the same network. If you need #OUT6 to depend on #OUT5, split into a fifth network or use SET / CLR instructions explicitly.
• Signal #IN4 is sampled twice. The CPU reads the input word twice within the same OB1 cycle. If #IN4 is wired to a fast sensor with sub-millisecond bounce, the FC could theoretically see two different values across the four reads. In practice the S7-300 input filter (default 6 ms for 24 V digital inputs) makes this extremely unlikely, but acknowledge it in your FMEA.
• Symbolic vs. absolute view. The original snippet uses # notation indicating FC/FB local interface symbols. If you switch to absolute display (View > Display > With Symbols off), #IN0 becomes I0.0 in this example. Re-symbolize after any paste to avoid mixing addresses.
• Know your FC return behavior. Local OUT parameters in an FC are by definition outputs, so the = assignment is the only write. If the parameter had been declared IN_OUT, the assignment would alter the caller's variable directly, and forgetting that difference is a common cause of "phantom" outputs on a HMI.

Verification: Proving the Interpretation Is Correct

1. Open the FC in STEP 7 and switch to the Monitoring / Debug view (Online > Monitor/Modify).
2. Force #IN4 = 0. Confirm all four outputs drop to 0 within one OB1 cycle.
3. Force #IN4 = 1. Then toggle each of #IN0 ... #IN3 independently and confirm the corresponding #OUTx follows without disturbing the other three outputs.
4. Use the Cross Reference tool (Ctrl+Shift+F in SIMATIC Manager) to verify there are no other writes to #OUT5 ... #OUT8 in the project. Double-writes are the leading cause of unexpected output behavior in networks like this.
5. Capture a trace with the S7-PDIAG or S7-GRAPH option, or with the free S7-Symbol Viewer, to record transitions of #IN4 against #OUT5 for a full shift.

Troubleshooting Matrix

Best-Practice Refactor: One Output per Network

Although the four-in-one STL is legal, most modern style guides for STEP 7 and TIA Portal recommend one logic step per network. Reasons include:

• Each network then converts to LAD/FBD without manual splitting.
• Network comments map 1:1 to signal descriptions in the user manual.
• Code reviewers can approve or reject each step independently in version control (e.g., SIMATIC Automation Tool, Git with the TIA Portal Openness interface).
• Cross-references and Go-to-Location work per-network, making troubleshooting faster.

If you choose to keep the compact form, add a network title such as "Step_Enable_4out_using_IN4_enable" and document the equation in the network comment so future maintainers do not have to decode accumulator state by hand.

Related STL Constructs Worth Knowing

FAQ