LOGO! Falling Edge Timer: Delayed Output with Auto-Reset

David Krause20 min read
PLC HardwareSiemensTutorial / How-to
Licensed PE Working through this on a live machine? A Maine-licensed engineer can take it from here — included with IMD hardware, by the hour for everything else. Book an engineer

Overview

Siemens LOGO! logic modules expose a catalog of timer blocks that all trigger on the rising edge of their trigger input. The platform does not provide a single block that begins timing on the falling edge of an input, counts a fixed interval, and asserts a latched output at the end of that interval. The behavior must be assembled from off-delay, on-delay, NOT, retentive on-delay, and latching relay blocks available in the LOGO! 8 function catalog.

This article documents the canonical three-block and four-block implementations for a falling-edge-triggered 2-second timer with auto-reset on a single digital input. The patterns are fully supported in LOGO! Soft Comfort V8.3 and later, execute within a single LOGO! scan cycle, and require no custom UDF (User-Defined Function) blocks. The article also documents a counter-based alternative for long delays, scan-time analysis, retention behavior across power cycles, and migration paths to SIMATIC S7-1200 for applications that exceed LOGO! resource limits.

Prerequisites

  • Siemens LOGO! 8 base module (6ED1052-1MD08-0BA2 or 6ED1052-2MD08-0BA2) with firmware V1.08.x or later. The "MD" suffix indicates the LOGO! 8.3 generation with Ethernet; the "2" prefix indicates the variant with transistor outputs.
  • LOGO! Soft Comfort V8.3 (6ED1058-0BA08-0YA1) or later installed on a Windows 10/11 PC
  • Ethernet (RJ45) or SD card connection between the PC and the LOGO! base module for program download
  • One digital input (I1) wired to a normally-open pushbutton or a process signal that transitions between 0 V and 24 V DC. The LOGO! 8 digital inputs are type 1 (IEC 61131-2) and accept 0-30 V DC with a guaranteed low threshold of 5 V DC and high threshold of 15 V DC.
  • One digital output (Q1) rated for the connected load. Relay-output variants switch 8 A at 250 V AC or 5 A at 30 V DC; transistor-output variants switch 0.3 A at 24 V DC.
  • Reference to the LOGO! 8 System Manual for block parameter details and the LOGO! product page for hardware specifications

Why No Native Falling-Edge Timer Exists

The IEC 61131-3 standard defines timer function blocks (TP, TON, TOF) with edge semantics that are explicit at the language level. LOGO! predates full IEC 61131-3 compliance in its block catalog and uses a simplified set of fixed-function blocks optimized for fast configuration by non-programmers. The LOGO! on-delay, off-delay, on/off-delay, and retentive on-delay all interpret a 0-to-1 transition on their trigger input as the timing event. A 1-to-0 transition is either ignored (TON, retentive TON) or used to start an off-delay countdown (TOF).

To build falling-edge timing, the 1-to-0 transition must first be converted to a 0-to-1 transition. The cleanest conversion uses an off-delay (B002) followed by a NOT gate (special B003 in the special functions family). The off-delay output stays high for T seconds after the input falls; the NOT output rises T seconds after the input falls. That rising edge is a valid trigger for any LOGO! timer or latching relay. The alternative conversion uses a NOT gate feeding the Trg input of a standard on-delay (B001); the NOT output rises when the input falls, and the on-delay triggers on that rising edge.

The LOGO! NOT gate (block B003 in the special functions family) is a pure logic inverter with no time base. It is not the same as the B002 off-delay in the timing family. Verify the block number before wiring—LOGO! Soft Comfort displays the block family and number in the block header.

LOGO! Timer and Logic Block Reference

The LOGO! 8 catalog exposes the following blocks relevant to falling-edge timing. Block numbers shown are for LOGO! Soft Comfort V8.3 and may differ on earlier versions.

Block Family Function Edge Behavior
B001 Timing On-delay (TON) Trigger on rising edge of Trg; output rises after T
B002 Timing Off-delay (TOF) Trigger on rising edge of Trg; output falls T after Trg falls
B003 Timing On/Off-delay (TON+TOF) Combines TON and TOF in one block
B004 Timing Retentive on-delay Trigger on rising edge; elapsed time survives power cycle
B005 Timing Wiping relay (pulse) Trigger on rising edge; output is a pulse of duration T
B006 Timing Edge-triggered wiping relay Trigger on rising edge; output pulse starts immediately
B007 Timing Symmetrical flashing relay Trigger on rising edge; output oscillates with 1:1 duty cycle
B003 (special) Special NOT gate Inverts the input signal; no time base
B008 (special) Special Latching relay (RS) Set on rising edge of S; reset on rising edge of R
B009 (special) Special Edge detection Generates one-cycle pulse on rising edge of Trg
B011 (special) Special Staircase lighting switch Off-delay with warning pulse and reset input

Source: LOGO! 8 System Manual, Chapter 4: Function Blocks.

Block Parameter Reference

Block Parameter Type Range Default
B001 (On-delay) T Time 0.01 s to 99 h 59 m 1.0 s
B001 (On-delay) Retention Boolean On / Off Off
B002 (Off-delay) T Time 0.01 s to 99 h 59 m 1.0 s
B002 (Off-delay) Retention Boolean On / Off Off
B004 (Retentive) T Time 0.01 s to 99 h 59 m 1.0 s
B004 (Retentive) Reset (R) Boolean On / Off Off
B008 (Latching) S input Boolean Edge-triggered —
B008 (Latching) R input Boolean Edge-triggered —
B008 (Latching) Retention (S) Boolean On / Off Off
B008 (Latching) Retention (R) Boolean On / Off Off

Solution 1: Three-Block Pattern (NOT + On-Delay + Latching Relay)

The minimal implementation uses three blocks. The pattern is preferred for new projects because it uses the fewest blocks, the most familiar timer type (on-delay), and the easiest-to-troubleshoot logic chain.

  1. NOT gate (special B003) inverts I1. Output INV_I1 is low while I1 is high and high while I1 is low.
  2. On-delay timer (B001) triggers on the rising edge of INV_I1. The rising edge of INV_I1 occurs when I1 falls. Output TIMER rises T seconds after I1 falls.
  3. Latching relay (special B008) is set by the rising edge of TIMER and reset by the rising edge of I1. Output Q1 follows the latched state.

For a 2-second falling-edge delay, set T = 2.0 s on B001. The complete signal chain is I1 → NOT → B001 → B008(S); I1 → B008(R); B008 output → Q1.

Parameter Table (Solution 1)

Block Parameter Value Notes
B003 (NOT) Input I1 No parameters
B001 (On-delay) Trg B003 output Rising-edge trigger
B001 (On-delay) T 2.0 s Falling-edge delay of I1
B001 (On-delay) Retention Disabled Not required for 2-s delay
B008 (Latching) S B001 output Set on rising edge of TIMER
B008 (Latching) R I1 Reset on rising edge of I1 (auto-reset)
B008 (Latching) Retention Enabled Preserves latched state across power cycles
Q1 Source B008 output Physical output

Signal Flow (Solution 1)

I1 NOT B001 On-Delay T=2.0s B008 Latching S: TIMER R: I1 Q: Q1 Q1

Solution 2: Four-Block Pattern (Off-Delay + NOT + Retentive On-Delay + Latching Relay)

This pattern uses an off-delay to extend the input pulse, a NOT gate to invert, a retentive on-delay to add a configurable post-falling-edge delay, and a latching relay to hold the output. It is functionally equivalent to Solution 1 but uses the retentive on-delay block, which preserves elapsed time across power cycles. The retentive on-delay is useful when the delay value is large (minutes or hours) and an unexpected power loss would otherwise require the operator to re-trigger the cycle.

  1. Off-delay (B002) triggers on the rising edge of I1. Its output OFF_DLY stays high for T_off seconds after I1 falls.
  2. NOT gate (special B003) inverts OFF_DLY. Output INV_OFF rises T_off seconds after I1 falls.
  3. Retentive on-delay (B004) triggers on the rising edge of INV_OFF. Output RET_DLY rises T_ret seconds after INV_OFF rises, which is T_off + T_ret seconds after I1 falls.
  4. Latching relay (special B008) is set by RET_DLY and reset by the next rising edge of I1.

For a 2-second falling-edge delay, set T_off = 1.9 s and T_ret = 0.1 s (or T_off = 2.0 s and T_ret = 0.01 s, the LOGO! minimum). The retentive on-delay's T_ret parameter controls the minimum pulse width presented to the latching relay's S input.

Parameter Table (Solution 2)

Block Parameter Value Notes
B002 (Off-delay) Trg I1 Rising-edge trigger
B002 (Off-delay) T_off 1.9 s Pulse extension after I1 falls
B002 (Off-delay) Retention Disabled Optional
B003 (NOT) Input B002 output No parameters
B004 (Retentive) Trg B003 output Rising-edge trigger
B004 (Retentive) T_ret 0.1 s Minimum S-pulse width
B004 (Retentive) Retention Enabled Survives power loss
B008 (Latching) S B004 output Set on rising edge of RET_DLY
B008 (Latching) R I1 Auto-reset on next I1 press
B008 (Latching) Retention Enabled Preserves latched state

Solution 3: Counter-Based Long-Delay Pattern

For falling-edge delays exceeding 99 h 59 m (the LOGO! timer maximum), the timer-based patterns must be replaced by a counter clocked from a known time base. The pattern uses a 1-Hz asynchronous pulse generator (B008 in the timing family) gated by the inverted input, and an up/down counter (B002 in the counter family) that latches the relay at the threshold count.

  1. Asynchronous pulse generator (timing B008) generates a 1-Hz square wave on its output PULSE.
  2. NOT gate (special B003) inverts I1. Output INV_I1 is high while I1 is low.
  3. AND gate (special B004) combines PULSE and INV_I1. Output CLK rises once per second while I1 is low.
  4. Up/down counter (counter B002) counts the rising edges of CLK. Its output rises when the count reaches the threshold N.
  5. Latching relay (special B008) is set by the counter output and reset by the next rising edge of I1.

For a 2-second delay, set the counter threshold to N = 2. For a 1-hour delay, set N = 3600. The counter resets on the next rising edge of I1, providing the auto-reset behavior.

The asynchronous pulse generator (B008 in the timing family) has a minimum period of 0.05 s (20 Hz). For sub-second timing resolution, use a faster time base or migrate to a SIMATIC S7-1200 with IEC timer blocks.

Timing Diagram

0s 0.5s 1.0s 1.5s 2.0s 2.5s I1 INV_I1 TIMER Q1 I1 falls (T0) TIMER rises (T0 + 2.0s) I1 rises (auto-reset)

Step-by-Step Configuration in LOGO! Soft Comfort V8.3

  1. Launch LOGO! Soft Comfort V8.3. Select File → New and choose the LOGO! 8 base module matching your hardware (for example, 6ED1052-1MD08-0BA2 for the LOGO! 8.3 with relay outputs).
  2. Open the block catalog in the right pane. Under Special functions, drag a NOT gate (special B003) onto the diagram canvas. Connect its input to I1.
  3. Under Timing, drag an On-delay (B001) onto the canvas. Connect its Trg input to the output of the NOT gate.
  4. Double-click the on-delay block. In the properties dialog, set T to 2.0 s. Set the time base to seconds. Leave retention disabled unless the application requires it.
  5. Under Special functions, drag a Latching relay (special B008) onto the canvas. Connect its S input to the on-delay output. Connect its R input directly to I1.
  6. Double-click the latching relay. Enable Retention on both the S and R paths if the latched state must survive a power cycle.
  7. Connect the output of the latching relay to Q1.
  8. Select Tools → Simulation (F5) to start the LOGO! Soft Comfort simulator. Toggle I1 high, then low, then high again. Verify that Q1 rises approximately 2.0 s after I1 falls and returns low on the next I1 rising edge.
  9. Select Tools → Transfer → PC → LOGO! (or write to SD card). Download the program to the physical module.
  10. Switch the LOGO! to RUN mode. Test with the physical pushbutton. Measure Q1 with a multimeter to confirm timing.

Verification Procedure

  1. Connect an oscilloscope or logic analyzer to I1 and Q1. A two-channel scope with 1 MΩ input impedance and 10 MHz bandwidth is sufficient.
  2. Press and release the pushbutton (I1 goes high for at least 100 ms, then low). Measure the time from the I1 falling edge to the Q1 rising edge. Expected value: 2.0 s ± 20 ms (one LOGO! scan cycle plus timer resolution).
  3. Press the pushbutton a second time. Measure the time from the I1 rising edge to the Q1 falling edge. Expected value: less than 50 ms (one or two LOGO! scan cycles).
  4. Cycle power to the LOGO! while Q1 is high. If retention is enabled on the latching relay, Q1 must remain high after the restart. If retention is disabled, Q1 must return to low.
  5. Repeat the test with I1 held high for 10 seconds, then released. The 2-second delay must still be measured from the falling edge, not from the start of the high pulse.
  6. Test the edge case: press the button twice within 100 ms (chatter). The latching relay should set once and remain set until the next deliberate press.

Scan Time Analysis

LOGO! 8 base modules execute a cyclic scan with a period determined by program complexity. For a program of 3-4 blocks plus I/O handling, the scan period is typically 5-10 ms. The timer resolution is 0.01 s (10 ms), so the scan period is not the limiting factor for a 2-second delay. For long delays (minutes or hours), scan time is irrelevant.

The dominant timing error is the discretization of the timer value. The on-delay (B001) updates its elapsed-time counter once per scan cycle, so the output transitions within one scan period of the theoretical trigger time. With a 10 ms scan and a 2.0 s delay, the error is at most 10 ms (0.5%).

Delay Range Timer Block Resolution Typical Error
0.01 s to 99.99 s B001 / B002 / B004 0.01 s ±10 ms
100.0 s to 999.9 s B001 / B002 / B004 0.1 s ±100 ms
1000 s to 99 h 59 m B001 / B002 / B004 1.0 s / 1.0 min ±1 s or ±1 min
Greater than 99 h 59 m Counter-based pattern Time base period ±1 pulse period

Retention Behavior Across Power Cycles

LOGO! 8 supports retention on a per-block, per-parameter basis. The retention attribute is independent for the S and R paths of the latching relay, the trigger and reset paths of the retentive on-delay, and the trigger path of the on-delay and off-delay. The following table summarizes the retention behavior of the three-block and four-block patterns under power-cycle conditions.

Pattern Block Retention Setting State After Power Cycle
Solution 1 B001 (On-delay) Disabled Elapsed time resets to 0; Q1 returns to low
Solution 1 B008 (Latching) Enabled (S and R) Q1 retains its latched state (high or low) across power cycle
Solution 2 B002 (Off-delay) Disabled Output falls immediately on power restore
Solution 2 B004 (Retentive) Enabled Elapsed time retained; if T elapsed was reached, output rises immediately on power restore
Solution 2 B008 (Latching) Enabled (S and R) Q1 retains its latched state

Retention consumes a small amount of non-volatile memory in the LOGO! base module. The LOGO! 8.3 base module provides 320 KB of program memory and 32 KB of retentive data memory. The three-block pattern uses less than 100 bytes of retentive memory; the four-block pattern uses less than 200 bytes.

Wiring and Electrical Specifications

The LOGO! 8 digital inputs are type 1 per IEC 61131-2. The guaranteed low input voltage is 0-5 V DC; the guaranteed high input voltage is 15-30 V DC. The input current at 24 V DC is typically 2.5 mA per input. The input capacitance is approximately 10 nF, which combined with the source impedance of the pushbutton or sensor creates an RC time constant that limits the maximum input transition rate. For a 1 kΩ source, the time constant is 10 µs, well below the LOGO! scan rate.

For mechanical pushbuttons, contact bounce can generate multiple transitions within 1-10 ms. The three-block and four-block patterns do not include debounce logic. If the application requires debouncing, insert a 50 ms on-delay (B001) on the I1 input path, with its output feeding both the NOT gate and the latching relay R input.

Signal Terminal (LOGO! 8.3 Relay) Terminal (LOGO! 8.3 Transistor) Wire Gauge Max Length
I1 (24 V DC input) I1 I1 0.5-1.5 mm² (20-16 AWG) 100 m shielded
Q1 (Relay output) Q1a / Q1b — 0.5-2.5 mm² (20-14 AWG) Per load spec
Q1 (Transistor output) — Q1+ / Q1- 0.5-1.5 mm² (20-16 AWG) 10 m shielded
24 V DC supply L+ / M L+ / M 0.5-2.5 mm² (20-14 AWG) Per supply spec

Integration with LOGO! TDE Display

The LOGO! TDE (Text Display, 6ED1055-4MH08-0BA0) is an optional external HMI for the LOGO! 8.3 base module. It connects via the second Ethernet port on the base module and provides a 6-line, 20-character backlit LCD. The TDE can display the state of I1, the NOT output, the on-delay output, and Q1 in real time. This is useful for field commissioning and troubleshooting without a PC.

To enable TDE display, open the LOGO! program properties in LOGO! Soft Comfort, select the Message text tab, and add a message text block that references I1, B001 output, and Q1. Configure the message text to update on every scan. The TDE will then show the live state of the falling-edge timer chain.

Troubleshooting Matrix

Symptom Probable Cause Remediation
Q1 rises immediately when I1 falls NOT gate is missing or wired incorrectly; B001 is triggered directly by I1 Verify the NOT gate is between I1 and the on-delay Trg input
Q1 never rises On-delay T set to 0 s, or latching relay S input is not wired Set T = 2.0 s; verify S input of B008 is connected to B001 output
Q1 rises but does not auto-reset Latching relay R input is not wired to I1, or I1 is held low Wire R input directly to I1; verify the pushbutton releases fully
Q1 timing is off by 100-200 ms LOGO! scan time added to the timing chain Reduce program block count; check for unused analog blocks that force slower scan
State lost on power cycle Retention not enabled on B008 latching relay Open B008 properties, enable Retention on both S and R parameters
Output chatters or double-triggers I1 contact bounce on the pushbutton Add a 50 ms on-delay (B001) on the I1 input path, or use a debounced input module
Error 0x01 in LOGO! diagnostic log Block parameter out of range or block not supported in current firmware Update LOGO! base module firmware to V1.08.x or later; verify block numbers match the LOGO! 8 catalog
Error 0x08 in LOGO! diagnostic log Program memory exceeded or block count exceeded Reduce block count; check the project info dialog for memory usage
Q1 stays high after R pulse Latching relay R input is being held high, masking the rising edge Verify R is a momentary signal; check for stuck-closed contact
Timer counts up but does not stop at T Wrong block type selected (e.g., B005 wiping relay instead of B001 on-delay) Verify block number; B001 is the on-delay, B005 is the wiping relay

Field Commissioning Checklist

  1. Verify the LOGO! base module firmware is V1.08.x or later using the LOGO! menu: Diagnostics → Module Info → Firmware.
  2. Verify LOGO! Soft Comfort version is V8.3 or later using Help → About.
  3. Download the program to the LOGO! via Ethernet (faster) or SD card (no PC required at the panel).
  4. Switch the LOGO! to RUN mode. The RUN LED must be solid green.
  5. Test the input by shorting I1 to 24 V DC with a jumper wire. Verify the input LED on the LOGO! illuminates.
  6. Remove the jumper. Measure the time from jumper removal to Q1 activation with a stopwatch or scope. Expected: 2.0 s ± 200 ms (stopwatch resolution).
  7. Re-apply the jumper. Verify Q1 turns off within 100 ms of jumper re-application.
  8. Cycle power to the LOGO!. If retention is enabled, verify Q1 retains its state. If retention is disabled, verify Q1 turns off.
  9. Document the wiring, the program version, and the test results in the project file.

Resource Limits and Migration

LOGO! 8 base modules support 200 (LOGO! 8.1 and earlier) or 400 (LOGO! 8.2 and later) function blocks. The three-block and four-block patterns consume 3-4 of that budget, leaving ample headroom for additional logic. Scan time on a small program is typically 5-10 ms on the 6ED1052-1MD08-0BA2 variant.

For applications that exceed 99 h 59 m (the maximum LOGO! timer value) or require millisecond-resolution timing, migrate to a SIMATIC S7-1200 CPU (for example, 6ES7214-1AG40-0XB0) and use the IEC 61131-3 TP (pulse) and TOF (off-delay) blocks in TIA Portal V17 or later. The IEC standard supports falling-edge-triggered timing via the TP block with inverted trigger input.

Feature LOGO! 8.3 S7-1200
Max function blocks 400 Limited by work memory (75 KB to 150 KB)
Max timer value 99 h 59 m 24 d 20 h 31 m 23 s (DWORD)
Min timer value 0.01 s 1 ms
Falling-edge timer support Manual (NOT + TON pattern) Native (TP with inverted Trg, or |N| contact)
Programming tool LOGO! Soft Comfort V8.3 TIA Portal V17 or later

LOGO! timer blocks cap at 99 h 59 m. For longer delays, cascade a 1-Hz time-base asynchronous pulse generator (B008 in the timing family) with an up/down counter (B002 in the counter family), or migrate to S7-1200.

Edge Detection in General Practice

The falling-edge detection pattern used in this article (NOT + edge-triggered timer) is a general technique in PLC programming. Many platforms, including SIMATIC S7-1200/1500 in TIA Portal, Allen-Bradley ControlLogix in RSLogix 5000 / Studio 5000, and Beckhoff TwinCAT 3, provide explicit falling-edge contact instructions (for example, -|N|- in ladder logic) that simplify the wiring. The LOGO! approach using a NOT gate and a rising-edge-triggered timer is functionally equivalent and translates directly when porting the program to other platforms.

For an Allen-Bradley ControlLogix migration, the equivalent logic uses an XIO (Examine If Open) contact on the falling-edge bit paired with an ONS (One-Shot) instruction feeding a TON timer. The output latches via an OTL (Output Latch) bit, and the auto-reset is implemented with an OTU (Output Unlatch) on the same rising-edge bit. The behavior is identical to the LOGO! pattern but uses native falling-edge detection primitives.

Safety Considerations

The patterns documented in this article are intended for non-safety control functions such as sequencing, lighting, and signaling. They are NOT rated for use in safety instrumented systems (SIS) per IEC 61508 or IEC 61511. For safety functions requiring SIL 1 or higher, use a LOGO! 8 safety variant (LOGO! 8.3 Safety, 6ED1052-1MD08-0BA2 with the "F" suffix firmware) or a SIMATIC S7-1200F safety PLC. The safety variants provide certified function blocks (emergency stop, safety gate monitoring, two-hand control) and must be programmed with the LOGO! Safety Tool add-in.

Do not use the standard latching relay (B008) for safety outputs. The LOGO! safety variants include a dedicated safety latching relay (B039) with integrated cross-fault detection and EDM (External Device Monitoring) support.

FAQ

Can a single LOGO! block start timing on a falling edge?

No. The LOGO! 8 catalog timer blocks (B001-B008) all trigger on the rising edge of the Trg input. Falling-edge-triggered timing must be constructed using a NOT gate (special B003) feeding the Trg input of a rising-edge timer, as documented in the three-block pattern above.

What is the minimum timer value in LOGO! 8?

The minimum time base in LOGO! Soft Comfort V8.3 is 0.01 s (10 ms). The on-delay (B001), off-delay (B002), and retentive on-delay (B004) all accept values from 0.01 s to 99 h 59 m.

How do I enable retention on a latching relay?

Open the latching relay (B008) properties dialog, select the Retention tab, and check the box for both the S and R parameter paths. The latched state will then survive a power cycle or a STOP-to-RUN transition.

Can I use one physical input for both the trigger and the auto-reset?

Yes. Wire the same input (for example, I1) to both the NOT gate input (or off-delay Trg input) and the latching relay R input. The off-delay and on-delay blocks are edge-sensitive and will not re-trigger on a sustained high level; the latching relay R input is level-insensitive and clears the relay on any rising edge.

Does this pattern work on LOGO! 6 or LOGO! 7?

Yes. The off-delay, on-delay, retentive on-delay, NOT gate, and latching relay blocks are available on all LOGO! generations from 0BA4 onward. Block numbers and the LOGO! Soft Comfort menu structure differ between LOGO! 6 (0BA6) and LOGO! 8 (0BA8), but the logic is identical. Refer to the LOGO! 8 System Manual for the current block numbering.

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