P0_2 and P0_3 can be assigned to FLEXCOMM3 transmit and receive functions on the LPC54016JET100. If USART3 produces no output, check the IOCON pin function, FLEXCOMM3 reset and clock controls, peripheral selection, and FLEXCOMM3 clock source before diagnosing higher-level serial code.
Configure the P0_2 and P0_3 Pin Multiplexing
Enable the IOCON and GPIO0 clocks before changing the pin configuration. Configure P0_2 as FC3_TXD and P0_3 as FC3_RXD by selecting pin function 1. The supplied configuration also enables the digital function and pull-up, disables inversion, input filtering, and open-drain operation, and selects standard slew-rate control.
#define IOCON_PIO_DIGITAL_EN 0x0100u
#define IOCON_PIO_FUNC1 0x01u
#define IOCON_PIO_INPFILT_OFF 0x0200u
#define IOCON_PIO_INV_DI 0x00u
#define IOCON_PIO_MODE_PULLUP 0x20u
#define IOCON_PIO_OPENDRAIN_DI 0x00u
#define IOCON_PIO_SLEW_STANDARD 0x00u
CLOCK_EnableClock(kCLOCK_Iocon);
CLOCK_EnableClock(kCLOCK_Gpio0);
uint32_t pin_config = IOCON_PIO_FUNC1 |
IOCON_PIO_MODE_PULLUP |
IOCON_PIO_INV_DI |
IOCON_PIO_DIGITAL_EN |
IOCON_PIO_INPFILT_OFF |
IOCON_PIO_SLEW_STANDARD |
IOCON_PIO_OPENDRAIN_DI;
IOCON_PinMuxSet(IOCON, 0, 2, pin_config); /* P0_2/FC3_TXD */
IOCON_PinMuxSet(IOCON, 0, 3, pin_config); /* P0_3/FC3_RXD */
Reset, Clock, and Select FLEXCOMM3
The supplied initialization sequence resets FLEXCOMM3 through bit 14 of PRESETCTRL[1], enables its gated clock through bit 14 of AHBCLKCTRL[1], writes 0x01 to FLEXCOMM3->PSELID, and selects FRO_12M for FLEXCOMM3 by writing 0x00 to FCLKSEL[3].
SYSCON->PRESETCTRL[1] |= (1u << 14);
SYSCON->PRESETCTRL[1] &= ~(1u << 14);
SYSCON->AHBCLKCTRL[1] |= (1u << 14);
FLEXCOMM3->PSELID = 0x01;
SYSCON->FCLKSEL[3] = 0x00; /* Select FRO_12M */
Resolve the Peripheral-Selection Ambiguity
The evidence assigns 0x01 to PSELID, but its adjacent comment says that FLEXCOMM3 is being set as SPI. That comment conflicts with the stated USART3 objective. Treat the value and comment as an ambiguity: verify that the selected PSELID value represents USART operation for the exact LPC54016JET100 documentation and software package before relying on the sequence.
| Item | Evidence-supported setting | Required check |
|---|---|---|
| P0_2 | Function 1, FC3_TXD
|
Confirm the mux write reaches port 0, pin 2 |
| P0_3 | Function 1, FC3_RXD
|
Confirm the mux write reaches port 0, pin 3 |
| FLEXCOMM3 clock |
FCLKSEL[3] = 0x00, identified as FRO_12M
|
Use this selected clock when configuring the USART rate |
| Peripheral selection | PSELID = 0x01 |
Resolve the conflicting SPI comment before use |
Verify the Configuration Sequence
- Enable the IOCON and GPIO0 clocks.
- Write the complete function-1 digital configuration to P0_2 and P0_3.
- Reset FLEXCOMM3 and enable its gated clock using bit 14 in the stated register banks.
- Select the FLEXCOMM3 peripheral mode, resolving the
PSELIDambiguity against the exact device documentation. - Select the FLEXCOMM3 clock through
FCLKSEL[3], then verify the USART configuration uses that clock source. - Transmit a message and check P0_2, the configured
FC3_TXDpin, for output.
FAQ
Which LPC54016JET100 pin carries USART3 transmit data?
The supplied mapping configures P0_2 as FC3_TXD using IOCON function 1. P0_3 is configured as FC3_RXD.
Which clocks must be enabled before configuring USART3 pins?
Enable kCLOCK_Iocon and kCLOCK_Gpio0 before calling IOCON_PinMuxSet. The sequence also enables the FLEXCOMM3 gated clock through bit 14 of AHBCLKCTRL[1].
Why must FLEXCOMM3 PSELID be checked when USART3 has no output?
The supplied sequence writes 0x01 to PSELID, while its comment describes SPI rather than USART. Verify the meaning of that value for the LPC54016JET100 before concluding that FLEXCOMM3 is operating as USART3.