Measuring 1 ms Pulse Duration on Siemens S7-300 CPU 314

Pulse-duration measurement on a Siemens SIMATIC S7-300 with a CPU 314 is a recurring field requirement: a discrete sensor (photo-eye, proximity switch, index marker, valve position) produces a short logic pulse and the application needs the on-time in milliseconds with a resolution of 1 ms. The default SIMATIC S5 timers shipped in STEP 7 / SIMATIC Manager have a 10 ms time base, so the obvious approach of using an IEC timer (SFB4/SFB5 TON/TOF) or a SIMATIC S5 timer (T0–T127) fails the 1 ms requirement by an order of magnitude. This reference shows three working methods to achieve 1 ms pulse-duration measurement: (1) an OB35 cyclic interrupt scheduled at 1 ms with edge latching, (2) an OB40 hardware interrupt triggered by a fast digital input module, and (3) the integrated high-speed counter / period-measurement functions of a CPU 314C. The trade-offs in scan time, input-filter delay, jitter, and OB priority are covered in depth so that the implementation matches the real signal rather than a textbook assumption.

1. Problem Definition and Application Constraints

Customer requirements typically state one or more of the following:

• Measure the on-time (positive-edge to negative-edge) of a 24 V DC logic pulse.
• Resolution of 1 ms (1 000 µs), often an absolute minimum, not just a desired resolution.
• Accuracy of ±1 ms or ±0.5 ms depending on the controller and OB priority class.
• Rejection of bounce, noise, and re-triggering from contact sensors.
• Update rate from 10 Hz to 1 kHz depending on the production cycle.

The naive solution is to start an S5 timer on the rising edge and stop it on the falling edge, then read the elapsed time. This fails for two independent reasons on a CPU 314:

1. The SIMATIC S5 timer T0 through T127 has a fixed 10 ms time base in the CPU 314 firmware. Pulses shorter than 10 ms cannot be resolved.
2. The default OB1 scan cycle is in the 5–20 ms range, so even a software-edge approach misses short pulses between scans.

The remedy is to (a) move the timing into a cyclic interrupt OB running at 1 ms and (b) use a digital input module whose input-filter delay is below the pulse width. The next sections cover the CPU, the input modules, and the OB configuration that together make 1 ms resolution achievable.

2. CPU 314 Hardware and Timing Limits

The CPU 314 (MLFB 6ES7 314-1AG14-0AB0 in its most common current revision) provides 128 KB of work memory, 0.06 ms per 1 000 bit-instructions, and 24 integrated digital inputs. Key timing-relevant parameters:

Two firmware-related facts matter for 1 ms measurement:

• Newer CPU 314 firmware exposes the system clock with 1 ms resolution via the SFC 0 / SFC 1 (SET_CLK / READ_CLK) and the SFC 64 TIME_TCK function. This is documented in the official Siemens support entry 16749674 — when you read the time of day with 1 ms resolution you can compute the delta between two edge timestamps directly. See Siemens Support Entry 16749674 – CPU 314 firmware time read.
• For pulses under ~5 ms the integrated DI filter (1.2 ms typ. / 4.8 ms max) on the CPU 314 front connector will attenuate the signal. A separate high-speed DI module is normally required.

3. Digital Input Module Selection

The input module determines the smallest pulse the PLC can even see. The S7-300 SM 321 family has several variants, and the input-filter delay varies from 25 µs to 4.8 ms. For 1 ms pulse measurement, the filter must be an order of magnitude below the pulse width, so modules in the 25–75 µs class are mandatory.

The two relevant modules for 1 ms measurement are:

• 6ES7 321-1BH10-0AA0 – 16 DI, 24 V DC, 1-wire, input delay 24 µs typical / 75 µs maximum. No hardware interrupt capability; the application must poll at 1 ms (OB35) to catch both edges. Used when the signal is guaranteed to be wider than 2 ms and CPU load is acceptable.
• 6ES7 321-7BH01-0AB0 – 16 DI, 24 V DC, with hardware interrupt generation. Configurable positive-edge / negative-edge masks per channel. This module raises a hardware interrupt that calls OB40 within microseconds, eliminating the need for constant OB35 polling of this signal.

Reference: S7-300 SM 321 module data and the S7-300 Module Data manual on the Siemens support portal.

4. Method 1 – OB35 Cyclic Interrupt at 1 ms

OB35 is the cyclic interrupt OB scheduled by the S7-300 CPU. The period is configured in HW Config → CPU properties → Cyclic Interrupts. The default is 100 ms, but the supported range includes 1 ms. The procedure is:

1. Open the S7 project in SIMATIC Manager, open HW Config.
2. Double-click the CPU 314 rail slot, select Cyclic Interrupts.
3. Set the OB35 execution period to 1 000 µs (1 ms). Be aware that OB35 with a 1 ms period consumes a significant fraction of the CPU 314's 0.06 µs/bit-instruction budget. Keep OB35 short – typically fewer than 20 STL statements – to avoid scan-time overruns.
4. Insert a new STL source or block, create OB35 in the project if it does not exist.
5. In OB35, read the input image of the fast SM 321 module, latch the previous state in a static flag, detect rising and falling edges, and accumulate the pulse width in a counter incremented every call.

The edge-detection logic in OB35 is straightforward. With OB35 called at 1 ms, every call represents 1 ms of pulse time:

// OB35 - called every 1 ms
// Inputs: I 0.0 = pulse input on SM 321 6ES7 321-1BH10-0AA0
// Flags: M 0.0 = previous state, M 0.1 = pulse in progress
//        MW 2 = pulse counter (ms), MW 4 = latched result (ms)

      L     I     0.0          // read pulse input
      T     MB    0            // current state into MB0 (bit 0)

      AN    M     0.0          // previous = 0?
      JC    NO_RISE            // no rising edge

      L     I     0.0          // current = 1?
      JN    NO_RISE

// Rising edge detected: start counting
      SET
      S     M     0.1          // pulse in progress
      L     0
      T     MW    2            // reset counter
      JU    END_OB35

NO_RISE: A     M     0.1         // pulse active?
      JC    COUNT
      JU    END_OB35

// Falling edge detected: latch result
COUNT: A     I     0.0           // input still high?
      JC    INC_COUNT
// Falling edge: store and stop
      L     MW    2
      T     MW    4             // latched result (ms)
      R     M     0.1           // clear in-progress
      JU    END_OB35

INC_COUNT: L     MW    2
      +     1
      T     MW    2             // counter++ each 1 ms

END_OB35: BE

Jitter on this method is bounded by the OB35 phase offset, typically ±200 µs on a CPU 314 with normal priority class. The achievable accuracy is therefore ±1 ms worst case, ±0.5 ms typical, which matches the original customer requirement.

5. Method 2 – OB40 Hardware Interrupt Capture

For signals that are too short to guarantee detection by OB35 polling, or for applications where the OB35 budget is already consumed, the SM 321 6ES7 321-7BH01-0AB0 module can generate a hardware interrupt on either edge. The CPU 314 calls OB40 in response. The principle:

1. Insert the SM 321 in HW Config.
2. Open the module properties, assign HW interrupt capability to the channel in use, and select the trigger edges (rising, falling, or both).
3. OB40 is called once per edge. Read OB40_MDL_ADDR (the module base address) and OB40_POINT_ADDR (the bit that triggered) to determine which channel caused the interrupt.
4. Use SFC 64 TIME_TCK or the system clock to time-stamp the interrupt. The delta between two timestamps is the pulse duration in 1 ms increments if you use the millisecond clock, or in 10 ms increments if you use the system time-of-day. Use the CPU 314 firmware that exposes the 1 ms clock as documented in Siemens Support Entry 16749674.

// OB40 - Hardware Interrupt
// Stamp arrival time on every call

      CALL  SFC   64            // TIME_TCK, returns system tick
       RET_VAL := MD  10        // tick in 1 ms after firmware update

      A     DB   10.DBX 0.0     // 'first edge seen' flag
      JC    FALL

// First edge (rising) - record start time
      L     MD   10
      T     MD   14             // pulse-start timestamp
      SET
      S     DB   10.DBX 0.0
      JU    END_OB40

FALL: // Falling edge - compute duration
      L     MD   10
      L     MD   14
      -D
      T     MD   18             // pulse duration in ms
      R     DB   10.DBX 0.0

END_OB40: BE

OB40 hardware interrupts are processed at a higher priority class than OB1 and lower than OB35 in the default S7-300 priority scheme. Check the priority assignments in HW Config and ensure that no lower-priority OB is starved by high-frequency interrupts — this is a common cause of field failures where the CPU enters STOP after several hours with OB80 (time error) or OB85 (priority class error).

6. Method 3 – CPU 314C Integrated Period Measurement

If the application can be migrated to a CPU 314C (MLFB 6ES7 314-6CG03-0AB0 or later), the integrated high-speed counters provide hardware-based period measurement with 1 µs resolution — an order of magnitude better than the 1 ms target. The four integrated counters can be configured in the following operating modes relevant to pulse measurement:

• Mode 0 – Single count, count internal pulses between external gates.
• Mode 1 – Single count with hardware gate.
• Mode 3 – Period measurement, where the CPU measures the time between two consecutive edges on the gate input.
• Mode 4 – Frequency measurement.

For pulse-duration measurement use mode 3, configure the gate as the pulse input, and read the measured period in the assigned data area (typically in the integrated I/O area starting at address 124 or higher, depending on the HW Config slot). The SFB 49 (frequency / period measurement block) reads the result. The 314C datasheet specifies 1 µs resolution for the integrated counters and gate frequencies up to 60 kHz. Reference: CPU 314C Compact manual.

7. Signal Conditioning and Wiring

A 1 ms digital pulse is sensitive to cabling, capacitance, and ground bounce. The following wiring rules apply:

• Use shielded twisted pair for the pulse line; ground the shield at one end only, at the PLC end.
• Keep the pulse line short – capacitive loading slows the edge and can make a 1 ms pulse look like a 2 ms pulse due to the low-pass effect of cable + input filter.
• For mechanical contacts (relay, microswitch) use an RC debounce or a digital debounce input module. A 1 ms pulse from a bouncing contact is not a 1 ms pulse.
• If the source is a PNP 24 V sensor, source the current into the SM 321 input. The 6ES7 321-1BH10-0AA0 is a sourcing (PNP) type 1 input per IEC 61131-2.
• Verify the 24 V DC supply with a scope at the module terminal. Sag under load is a frequent cause of "phantom" short pulses on commissioning day.

8. Configuration in STEP 7 / SIMATIC Manager

End-to-end commissioning steps for the OB35 method on a CPU 314 with SM 321 6ES7 321-1BH10-0AA0:

1. In SIMATIC Manager, open the S7 project and launch HW Config.
2. Add the CPU 314 in the appropriate slot. Configure Cyclic Interrupts → OB35 → Period = 1 000 µs.
3. Insert the SM 321 in slot 4 (recommended) and confirm the input-filter delay of 24/75 µs in the module's properties. Do not configure HW interrupt on this module – it does not support it.
4. Compile and download the hardware configuration.
5. Add an OB35 block to the Blocks container, write the edge-detection STL shown in Section 4, and download it to the CPU.
6. Force the CPU to RUN. Open VAT (variable table) and watch MW 4 while applying a test pulse from a calibrated pulse generator (e.g. a Beckhoff KL2408 driven at 1 ms).
7. Verify that the latched value MW 4 matches the applied pulse width within ±1 ms.

For the OB40 method with the 6ES7 321-7BH01-0AB0:

1. Insert the module, open properties → Inputs, and tick Hardware Interrupt for the channel in use. Select Both edges if both rising and falling edges are required.
2. Add an OB40 block and implement the time-stamp logic of Section 5.
3. Update the CPU 314 firmware to the revision referenced in Siemens Support Entry 16749674 if 1 ms clock resolution is required.
4. Download, run, and verify with a test pulse.

9. Verification and Commissioning Checks

Use the following checks to confirm 1 ms resolution is met in the field:

• Apply a 1 ms pulse from a bench pulse generator. The OB35 method should latch MW 4 = 1; the OB40 method should compute MD 18 = 1.
• Apply a 10 ms pulse. The OB35 method may latch between 9 and 11 ms (worst-case jitter of ±1 ms); the OB40 method with a 1 ms clock should latch 10 ±1 ms.
• Monitor the OB35 execution time with SFC 6 RD_SINFO or the system diagnostics; if the average exceeds 800 µs, OB35 will overrun at 1 ms period.
• Check the CPU diagnostic buffer for OB80 (time error) or OB85 (priority class error) entries. Frequent OB80 entries indicate OB35 is too long for the 1 ms period.
• Scope the pulse at the SM 321 input terminal to confirm that the input filter is not the limiting factor. The signal at the terminal must be at least 200 µs above the input-filter delay threshold.

10. Field-Proven Caveats and Troubleshooting Matrix

11. Comparison of the Three Methods

FAQ