Migrating CQM1 Encoder Cam Logic to Modicon M221 HSC

James Nishida8 min read
Motion ControlOmronTechnical Reference
Licensed PE Working through this on a live machine? A Maine-licensed engineer can take it from here — included with IMD hardware, by the hour for everything else. Book an engineer

Overview: What the CQM1 Program Is Actually Doing

A mid-1990s Omron CQM1 running an encoder-driven cam programmer must be retrofitted to a Schneider Electric Modicon M221. Before any M221 code is written, the legacy logic has to be decoded exactly, because the whole machine sequence hangs on four elements:

  • The DM6642 PLC Setup word (value 100 as read on the programming tool), which enables and configures the built-in high-speed counter.
  • Encoder inputs on the first input words: IR 000, IR 001, IR 002 are referenced by the application.
  • A first-scan preset pair: MOV 230 → DM0100, MOV 0 → DM0101, then INI(61) to load the counter present value (PV) and enable counter evaluation.
  • BCMP(68) comparing the counter source word against 16 range pairs starting at DM0000, writing the result bit map into HR00.

The result is a software cam switch: one instruction converts the encoder position into up to 16 zone bits. Each bit is a cam segment output.

Decoding the Block-by-Block Logic

Rung element Function Retrofit relevance
MOV #230 → DM0100 (first scan) Loads the low word of a 2-word (32-bit) preset buffer Becomes the HSC preset / reload value on the M221
MOV #0000 → DM0101 (first scan) Loads the high word of the same preset buffer Confirms the preset is a 32-bit quantity, upper word zero
INI(61) (first scan) Writes DM0100/DM0101 into the high-speed counter PV and starts comparison/evaluation Equivalent to the M221 HSC preset-load + enable
BCMP(68) source, DM0000, HR00 Block compare: source word against 16 lower/upper limit pairs Replaced by HSC thresholds or a comparison routine

The BCMP range table

BCMP(68) consumes 32 consecutive words as 16 range pairs. The mapping is strictly positional:

Lower limit Upper limit Result bit
DM0000 DM0001 HR00.00
DM0002 DM0003 HR00.01
DM0004 DM0005 HR00.02
DM0012 DM0013 HR00.06
DM0014DM0031 HR00.07HR00.15

Result logic per pair: source < lower limit → bit = 0; lower ≤ source ≤ upper → bit = 1; source > upper → bit = 0. In this machine only DM0000DM0013 carry cam values, i.e. seven active segments driving HR00.00HR00.06.

Critical: BCMP(68) always reads all 32 words. If DM0014DM0031 are not zero (or are retained garbage from an earlier program version), bits HR00.07HR00.15 can toggle unpredictably. Dump those 18 words from the running machine before you decommission it, and either replicate them or explicitly ignore bits 7–15 in the M221 code.

Resolving the "230" Ambiguity

Two readings of the number 230 are circulating, and they lead to completely different M221 designs. Do not pick one silently — test it.

Interpretation Consequence Plausibility check
230 is a literal constant used as the BCMP source HR00 would be a fixed bit pattern that never changes — a cam programmer that cannot move Functionally meaningless on a running machine; reject unless monitoring proves HR00 is static
230 is the counter preset written to DM0100, and the BCMP source is a word address holding the encoder PV (e.g. IR 230 or the equivalent PV word for this CPU) HR00 tracks shaft position; cam segments switch as the encoder turns Consistent with the observed cam values in DM0000DM0013

Verify on the live machine before the swap:

  1. Open a data monitor on the BCMP source operand and jog the machine by hand. If the value follows the shaft, the source is the counter PV word, not a constant.
  2. Cross-reference DM6642 in the program listing. If nothing writes it, the value came from the PLC Setup and is read at power-up only.
  3. Confirm the CPU model suffix (the CQM1-CPU__ part number). High-speed counter capability and the PV storage word depend on the CPU variant; check the operation manual for that exact model rather than assuming.
  4. Record whether the counter is configured for incremental (up/down) or up/down phase-difference (quadrature) operation, and whether the Z input performs a reset.

DM6642 and the input assignment

DM6642 is part of the CQM1 PLC Setup area. Setup words are read at power-up, so a change requires a power cycle to take effect — and a value read as 100 on the tool may be displayed in hexadecimal or decimal depending on the monitor format. Note the display base before you convert it. The referenced inputs IR 000, IR 001, IR 002 occupy the dedicated high-speed input positions; on a quadrature setup these carry phase A, phase B and the Z/marker pulse. Confirm the physical wiring at the terminal block and the encoder output type (push-pull, open collector, line driver, 12 V or 24 V) — this determines the M221 input hardware you need.

Mapping the Function to the M221

The M221 provides high-speed counter function blocks configured in EcoStruxure Machine Expert – Basic. Verify the following against the Modicon M221 Logic Controller Programming Guide and the hardware guide for your exact reference, because HSC channel count, maximum frequency and dedicated input positions vary by controller reference.

CQM1 element M221 equivalent Action required
DM6642 setup word HSC object configuration (counting mode, single/dual phase) Set quadrature vs. pulse mode to match the encoder
IR 000/IR 001 A,B Dedicated fast inputs assigned to the HSC channel Wire A/B to the fixed HSC input terminals; standard inputs will not work
IR 002 Z HSC preset/sync input Use for one-per-revolution re-sync of the position value
INI(61) preset load (230) HSC preset value + enable bit Load 230 as the preset; drive the enable from an init/first-scan bit
DM0000DM0013 cam table Memory words holding limit pairs Transfer the exact values; do not round
BCMP(68)HR00 Comparison routine writing a memory word bit map Reproduce the "in range = 1" semantics per pair
HR00 retentive behaviour Memory word declared retentive Only if the machine relies on retained cam state at power-up

Reproducing BCMP on the M221

The M221 has no single block-compare instruction with identical semantics. Implement the seven active segments as an explicit comparison, using the counter current value in place of the CQM1 PV word:

(* Position source: HSC current value copied to %MW200 each scan *)
%MW200 := %HSC0.V;

(* Segment 0: DM0 / DM1 -> HR0.0 *)
%M100 := (%MW200 >= %MW0) AND (%MW200 <= %MW1);
(* Segment 1: DM2 / DM3 -> HR0.1 *)
%M101 := (%MW200 >= %MW2) AND (%MW200 <= %MW3);
(* ... repeat through Segment 6: %MW12 / %MW13 -> %M106 *)

If a downstream routine expects the packed word, rebuild it bit by bit into %MW210 using the bit-access notation %MW210:X0%MW210:X6, mirroring the original HR00 layout. Keep the same bit order so that any documented output mapping remains valid.

Rollover trap: the CQM1 preset of 230 with a zero high word implies the position counter was intended to run over a bounded range, most likely reset each revolution by the Z pulse. On the M221, define explicitly whether the HSC free-runs and wraps at its full range or is re-synced at the marker. A free-running counter will drift out of every cam window after one wrap and the machine will appear to "lose" all cam outputs.

Commissioning and Verification

  1. Capture the baseline. Upload the CQM1 program and dump DM0000DM0031, DM0100, DM0101 and DM6642. Photograph the encoder terminal block and record the encoder pulses-per-revolution from its nameplate.
  2. Log live behaviour. With the machine running at normal speed, record the counter source word and HR00 together. Note the exact position value at each cam transition — this is your acceptance criterion, independent of any interpretation of the code.
  3. Static test on the M221. With the drive locked out, force %MW200 through the full range and confirm each segment bit turns on and off at the recorded limits, inclusive of both endpoints (the CQM1 test is and , not strict inequality).
  4. Direction and edge test. Turn the encoder by hand forward and reverse. The count must increment forward and decrement in reverse. If it counts backwards, swap A and B; if it counts only in one direction, the channel is configured for single-phase pulse counting instead of quadrature.
  5. Marker test. Rotate through the Z pulse and verify the position value re-syncs to the intended preset every revolution with no cumulative drift over 20+ revolutions.
  6. Speed test. Run at maximum machine speed and compare the pulse rate (PPR × rev/s) against the HSC maximum input frequency for your M221 reference. Miscounting at speed with correct counting at low speed points to frequency limits, input filtering, or encoder cabling/shielding.
  7. Overlap check. Confirm that segments intended to be mutually exclusive never assert simultaneously, and that no gap exists between adjacent segments where all bits fall to 0.

One further option worth pricing before committing to the retrofit: if only two or three machines run Omron and the rest of the plant is Schneider, standardising on the M221 is justified on spare parts and skills alone. If instead the goal is minimum engineering risk, a later-generation Omron CPU keeps the counter semantics closer to the original and eliminates the transcription errors that come with retyping cam tables by hand. Weigh the two against how much of the remaining program logic must also be rewritten.

FAQ

What does INI(61) do on a CQM1 high-speed counter?

It writes a new present value into the high-speed counter from a two-word source (here DM0100 low word = 230, DM0101 high word = 0) and starts counter comparison/evaluation. It is typically executed once on the first scan from a first-cycle flag.

How does BCMP(68) map results into HR0?

BCMP reads 32 consecutive words as 16 lower/upper limit pairs. Pair DM0000/DM0001 sets bit 00 of the result word, DM0002/DM0003 sets bit 01, and so on. A bit is 1 only when the source value is inside the inclusive range, otherwise 0.

Is 230 a value or an address in this program?

Both readings exist. As the operand moved into DM0100 it is a preset value; as a BCMP source it would have to be a word address holding the encoder present value, because a constant source would freeze HR00 into a fixed pattern. Monitor the operand while jogging the shaft to settle it.

Why must DM6642 be changed with a power cycle?

DM6642 belongs to the CQM1 PLC Setup area, which the CPU reads at power-up. Editing it while running has no effect on high-speed counter operation until the controller is power-cycled.

Can standard M221 inputs be used for the encoder?

No. Quadrature counting must use the controller's dedicated high-speed inputs assigned to the HSC channel. Check the maximum counting frequency for your specific M221 reference against encoder PPR multiplied by maximum shaft speed.

Back to blog