Migrating S7-200 Micro/WIN Programs to TIA Portal V13 Complete

David Krause18 min read
SiemensTIA PortalTutorial / How-to
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Overview of the Micro/WIN to TIA Portal Migration Challenge

Migrating an S7-200 program authored in STEP 7 Micro/WIN to TIA Portal V13 is a recurring engineering task whenever an older S7-200 CPU is being replaced by an S7-1200 or S7-1500. There is no supported automated converter in TIA Portal V13 that imports .mwp project files, and the legacy Micro/WIN-to-TIA migration add-on (originally bundled with early TIA V10/V11 releases) has been discontinued by Siemens. Field experience consistently shows that the legacy tool produced incomplete conversions: symbol tables were lost, subroutines (SBR) and interrupt routines (INT) were flattened into a single OB1 with no clear mapping, and any program using Freeport, USS, or Modbus RTU master libraries on the S7-200 required a complete rewrite anyway because the instruction set and library architecture differ substantially between the two platforms.

This guide consolidates a manual, deterministic conversion workflow that an automation engineer can follow without depending on deprecated utilities. It covers the platform architectural deltas, the hardware migration path from S7-200 to S7-1200/S7-1500, the address and data-type remapping rules, the serial communication re-implementation, and the verification steps required before powering up production hardware.

Engineering rule: Treat any legacy S7-200 Micro/WIN program as a functional specification, not as source code to be ported line-for-line. The fastest path is a clean re-implementation in TIA Portal V13 that preserves I/O behaviour and timing, not literal ladder rung text.

Platform Architecture: Micro/WIN vs TIA Portal V13

STEP 7 Micro/WIN is a 32-bit Windows programming environment for the SIMATIC S7-200 family. It uses a flat project model: one CPU per project, a single Program Block containing OB1 plus optional subroutines (SBR0..SBR31) and interrupt routines (INT0..INT31), a symbol table, a status chart, a data block, and a cross-reference. TIA Portal V13 is a multi-device, multi-controller engineering framework supporting S7-1200, S7-1500, ET 200, HMI panels, drives, and SCADA stations inside a single project. The program model is hierarchical: each PLC contains an OB folder with organisation blocks (OB1, OB100, OB82, etc.), one or more FB, FC, DB, and UDT objects, plus a project-wide PLC tag table.

Table 1 — Project structure differences between Micro/WIN and TIA Portal V13
Element STEP 7 Micro/WIN TIA Portal V13
Project container Single .mwp file per CPU Multi-device .ap13 project
Main scan OB1 (single) OB1 (cyclic), OB100 (warm restart), OB82 (diagnostic)
Subroutines SBR0..SBR31 called by CALL FC (no instance DB) or FB (with instance DB), called via CALL / multi-instance
Interrupts INT0..INT31 (timed, I/O, HSC, PTO) OB10..OB17, OB30..OB38 (cyclic), OB40..OB47 (HW interrupt), OB121/OB122 (error)
Symbols Symbol table (global) PLC tag table (DB-bound, I/O-bound, or local)
Data V-memory only (no DB concept) Optimised or standard DBs with UDTs
Libraries USS, Modbus, Recipe, Position, acc. wizard outputs TIA library "Communication_modular_Master" etc., or self-authored FB/FC

The single most consequential difference is the move from V-memory as global scratchpad to a typed DB model. In Micro/WIN you frequently see patterns such as VW100 used as a holding register, integer counter, or string buffer, with no naming or type information. In TIA Portal V13 each storage location should belong to a structured tag, ideally a UDT, so HMI faceplates, motion functions, and cross-references resolve correctly.

Prerequisites

  • Source artefact: the original .mwp file exported from Micro/WIN V4.0 SP9 (the final release; build 4.0.9.25 or later). Open the project, export the symbol table as File > Export > Symbol Table (CSV) and the data block as File > Export > Data Block (CSV). These exports become your authoritative tag inventory.
  • Target TIA Portal: V13 SP1 or V13 SP2 with the matching firmware support packages installed. The S7-1200 CPU you intend to deploy must be listed in the TIA V13 device catalogue (firmware ≤ V4.x for S7-1200). S7-1500 CPUs with firmware V1.5 or later require TIA V13 SP1 Update 4 or V13 SP2; check the SIMATIC S7-1500 CPU 1511-1 PN compatibility list before committing.
  • Hardware selection: an S7-1200 replacement CPU must be picked first, because the tag table, OB structure, and firmware capabilities all depend on the target model. Use the migration table in the next section.
  • Documentation: paper or PDF printouts of every Micro/WIN rung, subroutine, and interrupt routine. TIA Portal cannot read the .mwp archive, so the printed or PDF ladder is the working specification.
  • Test stand: a controlled environment with the target CPU, the equivalent S7-200 I/O wired or simulated, and the operator panel configured, before cutting over the production line.

Hardware Migration Path: S7-200 to S7-1200 / S7-1500

The S7-200 is end-of-life but still widely deployed. The pin-compatible successor for most applications is the S7-1200, but there are electrical and firmware caveats. Use the following mapping as a starting point.

Table 2 — S7-200 CPU to S7-1200/1500 replacement candidates
S7-200 source Typical application S7-1200 target S7-1500 target (if higher perf needed)
CPU 221 (6ES7210-0AA23-0XB0) Tiny relay-replacement CPU 1211C DC/DC/DC (6ES7211-1AE40-0XB0) —
CPU 222 (6ES7210-1AB23-0XB0) Small machine CPU 1212C DC/DC/DC (6ES7212-1AE40-0XB0) —
CPU 224 / 224XP (6ES7210-2AD23-0XB0 / ...0XB0) Mid-size machine, analog CPU 1214C DC/DC/DC (6ES7214-1AG40-0XB0) or 1215C CPU 1511-1 PN (6ES7511-1AK02-0AB0)
CPU 226 (6ES7210-2BD23-0XB0) Larger machine, 2 ports CPU 1215C DC/DC/DC (6ES7215-1AG40-0XB0) CPU 1513-1 PN (6ES7513-1AL02-0AB0)
CPU 226XM 40 kB work memory CPU 1217C (6ES7217-1AG40-0XB0) CPU 1515-2 PN (6ES7515-2AM02-0AB0)
Electrical pinout warning: The S7-200 24-pin ribbon connector and the S7-1200 front connector are not the same footprint. You must rewire the I/O terminals or use a migration terminal block kit (e.g. Siemens 6ES7292-1AB40-0XA0) if your plant cannot tolerate a re-wire. Always check the input voltage ranges: the S7-200 224XP analog inputs accept ±10 V, while the S7-1200 onboard analog inputs accept 0..10 V only — bipolar transducers must be re-ranged or buffered.

For S7-1500 migrations use the S7-1500 system manual as the authoritative reference. Memory and OB response times are an order of magnitude better than the S7-200, so scan-time tuning is rarely needed; the focus instead moves to deterministic PROFINET IO update times.

Addressing and Data Type Remapping

Every V, M, I, Q, AI, AQ, T, C, HC, S, and SM reference in the Micro/WIN program must be migrated to a TIA Portal tag. The rules below cover the cases you will encounter most often.

Table 3 — Address migration rules from S7-200 to S7-1200
Micro/WIN address Meaning TIA Portal V13 equivalent Notes
I0.0..Ix.7 Digital input byte x %Ix.0 in default tag table Filter input (50 µs) is configurable in CPU properties; default differs from S7-200 (0.2 ms)
Q0.0..Qx.7 Digital output %Qx.0 Output current rating: S7-1200 sink/source = 0.5 A/channel, S7-200 = 0.75 A. Check load
VW100, VD200 V-memory word / double-word Symbol in a global DB (e.g. "DB_Data".vwSpare100) or PLC tag "vwSpare100" Always declare a type (INT, REAL, DWORD) — never use raw BYTE in TIA
MB0..MB31 Flags / Merkers %Mx.0 in the default tag table or a global Merker-DB 128 bytes available by default on S7-1200
SMB28 / SMB29 Potentiometer values No equivalent — use analog input or remove S7-1200 has no onboard analog potentiometers
HC0..HC5 High-speed counter HSC function block inside OB / process interrupt OB40 Counter mode setup is wizard-driven on S7-1200 (Hardware ID, not address)
C0..C255 Counter word IEC counter (CTU, CTD, CTUD) inside a global DB Counts above 32 767 require DINT (LREAL for very large counts)
T0..T255 100 ms / 10 ms timers IEC timer TP / TON / TOF Resolution is now 1 ms and stored in a DINT; update timing logic
AIW0 / AQW0 Analog input/output word %IW from analog input module Channel selection now lives in the device configuration
SM0.0 / SM0.1 / SM0.5 Always-ON / first-scan / 1 Hz clock No direct equivalent — use a global DB bit set in OB100 (first scan) and OB1 (always-ON) SM bits have no clone in TIA; recreate explicitly
VB0..VB1023 (SMB area) Special memory Replaced by system clock bits, hardware-ID-based diagnostic OBs, or explicit logic Refer to S7-1200 system manual, section on system and clock memory

A pragmatic convention is to create one global DB called DataBlockGlobal that absorbs all of the renamed V-memory locations. This gives you a single watch table for commissioning and a single cross-reference for fault-finding, which the S7-200 program never had.

Instruction Set Differences

Most bit-logic instructions translate one-to-one: A (NO contact), AN (NC contact), = (coil), S/R (set/reset). Micro/WIN also offers immediate I/O instructions (e.g. IIL, SI) that bypass the process image update. In TIA Portal the equivalents are :%Ix.0: syntax inside the rung or, more idiomatically, calls to "READ_PI" / "WRITE_PI" system FBs.

Table 4 — Common Micro/WIN instructions and their TIA Portal V13 equivalents
Micro/WIN instruction Function TIA Portal V13 implementation
NETR / NETW Master read/write on Ethernet (PPI/MPI) No equivalent — use TSEND_C/TRCV_C with a TCP connection, or Modbus FB if the peer is Modbus TCP
XMT / RCV Freeport ASCII / RTU send/receive "Serial_Send_Block" from CM 1241 library, or Send_P2P / Receive_P2P FBs
PLS Pulse-train output CTRL_PTO / CTRL_PWM hardware-ID based, in process interrupt OB
HDEF / HSC High-speed counter setup / run Wizard-generated HSC instance DB plus CTRL_HSC_EXT FB
ATCH / DTCH / ENI / DISI Interrupt attach / detach / enable / disable Attach HW interrupts via device configuration; enable via "ATTACH" / "DETACH" system FBs
SBR Subroutine FC (no instance DB) or FB (with instance DB)
Read/Write Real-Time Clock (READ_RTC, SET_RTC) RTC access Use system time and WR_SYS_T / RD_SYS_T
FOR / NEXT Loop Same FOR / NEXT inside SCL or ladder — TIA V13 also supports REPEAT..UNTIL in SCL
SHRB / SHL_B / SHR_B Shift register Bit-string operations in SCL, or a self-built FB that wraps the shift on a DWORD
DECO / ENCO Decode / encode Implemented manually in SCL using a CASE or FOR loop; no direct ladder instruction
STR_CAT / STR_LEN String functions SCL CONCAT, LEN, FIND, MID

Serial Communication Migration (Critical Path)

The serial interface is the single biggest source of conversion failure. S7-200 Freeport on the RS-485 port uses a different byte-handshake model from S7-1200 point-to-point on the CM 1241 (RS-232 / RS-422 / RS-485) or CB 1241 (RS-485) communication modules. If the legacy program uses the USS protocol (drives), Modbus RTU master/slave, or a vendor-specific ASCII protocol, expect to re-author those code paths from scratch.

Freeport to Send_P2P / Receive_P2P

The Micro/WIN XMT and RCV instructions use the SMB30/SMB130 control byte plus an interrupt-driven RCV completion. The S7-1200 equivalent is the "Send_P2P" / "Receive_P2P" FB pair from the PtPCom library (part of the standard TIA V13 installation). Configure the CM 1241 module under Device configuration > Properties > Port configuration for the correct baud rate, parity, and flow control, then call the FB:

// SCL inside OB1, S7-1200 example
// "CM1241_1_DB" is the instance DB generated by the PtP wizard
#instSend(REQ := bSendRequest,
          LADDR := 271,                  // HW identifier of the CM 1241
          PORT := 0,
          DATA := sTxBuffer,             // VARIANT pointing to a DB area
          DONE => bSendDone,
          ERROR => wSendError,
          STATUS => wSendStatus);

#instRcv(EN_R := TRUE,
         LADDR := 271,
         PORT := 0,
         DATA := sRxBuffer,
         LEN := 0,
         DONE => bRcvDone,
         ERROR => wRcvError,
         STATUS => wRcvStatus);

Status word wSendStatus follows the S7-1200 common error code map; for example 16#8001 means the port is busy (another transmission is in progress), 16#80A1 indicates a parameter error in the LADDR assignment, and 16#80B0 signals a parity/framing overrun on the receiver. Cross-check these against the S7-1200 system manual PtP appendix.

USS to USS_Port_Scan / USS_Drive_Control

If the S7-200 program is running drives over USS, swap the wizard-generated USS_INIT and USS_CTRL for the USS_Port_Scan and USS_Drive_Control FBs from the USS library. The drive address mapping (1..32) is identical, but the S7-1200 variant uses symbolic instance DBs instead of the S7-200's global V-memory block at VW1000. Plan to rename every V-memory reference that was reserved by the Micro/WIN USS wizard.

Modbus RTU Master to Modbus_Master_P2P

For Modbus RTU master, use the "Modbus_Master_P2P" FB shipped with TIA V13. It supports function codes 1, 2, 3, 4, 5, 6, 15, and 16 out of the box. The required scan/poll period must be increased from the S7-200 typical 50..200 ms to at least 100 ms on S7-1200 to avoid overloading the serial port when more than eight slaves are present.

Timing trap: The S7-200 RCV instruction accepts any data without timeout enforcement at the application layer. The S7-1200 Receive_P2P has a configurable end-of-message detection (line idle time, character timeout, or max length). If you set the wrong detection mode, the master never receives a complete telegram. Always verify with a Modbus scanner tool on the bench before commissioning.

Manual Conversion Procedure: Step-by-Step

  1. Audit the source. Open the .mwp in Micro/WIN V4.0 SP9. Cross-reference every subroutine and interrupt, then print the entire project to PDF. Note the byte offset of every V-memory reference by sorting the symbol table by address.
  2. Inventory the hardware. List every S7-200 model, EM expansion module, and CP (e.g. CP 243-1, CP 243-2 AS-Interface, EM 277 PROFIBUS). Cross-check against the S7-1200/1500 family: not every CP has a 1:1 replacement. For PROFIBUS, the S7-1200 needs a CM 1243-5 master or CM 1242-5 slave module; the EM 277 GSD file is compatible after a firmware re-flash.
  3. Select the target CPU. Use Table 2 as the starting point. Confirm program memory: an S7-200 program that fills 16 KB of V-memory typically consumes 30..40 KB of work memory on the S7-1200 once UDTs and FBs are added. Order a CPU with sufficient load memory — typically 1215C for mid-range projects.
  4. Build the new project. In TIA Portal V13, create a new project, add the target CPU, configure PROFINET or PROFIBUS devices, and set the IP address. Compile the empty project first; this catches device catalogue errors before you spend hours on logic.
  5. Create the global tag table. Import the Micro/WIN symbol export (CSV) into the PLC tag table via Edit > Import/Export. TIA V13 honours the column structure: Name | Path | Data Type | Address | Comment. Re-type all V-memory symbols to use the new DB-prefix convention.
  6. Author a global DB to absorb V-memory. For each symbol that previously lived in V-memory, add a typed tag inside a single global DB named, for example, "DB_Migrated". Replace every VWx with "DB_Migrated".tag. Doing this in one pass preserves the program semantics and produces a clean watch table.
  7. Translate OB1. Open the printed Micro/WIN OB1 PDF and re-author the rung-by-rung logic inside the TIA Portal OB1. Use the FBD/LAD view, or switch to SCL for blocks that benefit from structured text (string handling, math, loops). Maintain rung comments — they are the only documentation the next engineer will inherit.
  8. Convert subroutines to FC / FB. Each Micro/WIN SBR becomes an FC in TIA Portal. Convert any SBR that carried persistent state (e.g. a state machine flag) into an FB with an instance DB, then call it via a multi-instance inside OB1.
  9. Re-implement interrupts. Time-driven Micro/WIN INTs become cyclic OBs (OB30..OB38). I/O-driven INTs become hardware-interrupt OBs (OB40..OB47). For PTO pulse-train output, use CTRL_PTO triggered from OB1 or a cyclic OB. For HSC, use the HSC wizard to generate the instance DB and call CTRL_HSC_EXT from OB1.
  10. Re-implement serial communication. As detailed in the previous section: XMT/RCV → Send_P2P/Receive_P2P; USS_INIT → USS_Port_Scan; Modbus RTU master → Modbus_Master_P2P.
  11. Re-implement PID loops. The Micro/WIN PID wizard writes a self-contained loop into V-memory and an INT routine. In TIA Portal use the PID_Compact (S7-1200) or PID_Basic block, configured from the technology object tree.
  12. Compile and download. Use TIA Portal Compile > Software (rebuild all blocks). Resolve any address conflicts (TIA will refuse to compile overlapping tags). Download to the target CPU in STOP mode, then perform a warm restart.

Verification and Commissioning

Manual conversion is only as good as its test coverage. Use the following verification sequence before touching production hardware.

  1. Offline simulation. Open the TIA Portal PLCSIM instance of the target CPU. Force every input from the watch table, and step through OB1 with breakpoints. Confirm that the V-memory-to-DB migration produced no off-by-one errors (a classic mistake is forgetting that VW100 and VB101 overlap, while the equivalent INT tag in a DB does not).
  2. Online cross-reference. Open Project tree > PLC > Cross-reference in TIA Portal and verify that every Micro/WIN reference has a counterpart. Any address used by Micro/WIN that is no longer used in TIA should be a red flag — it may have been silently lost during translation.
  3. Scan-time audit. Monitor OB1 execution time under worst-case load. S7-1200 OB1 typically runs at 1..10 ms; the S7-200 was often 20..50 ms. If the production timing depended on the slow scan, retune any filter or debounce logic.
  4. I/O loop-back. With the actual wiring in place, force every output from the watch table and confirm the corresponding physical action. Then read back every input via the watch table and confirm the expected state. Document each verified point on the test sheet.
  5. Communication smoke test. Run a Modbus/USS/serial trace on the bench. Compare the raw telegrams byte-for-byte against a capture from the legacy S7-200 with the same payload. Any difference in byte order, CRC, or inter-character timing will produce a fault downstream.
  6. Fault injection. Pull the PROFIBUS connector, disconnect a sensor, or short an output. Confirm that the diagnostic OB82 fires and the HMI displays the expected alarm. The S7-200 had only SM bit flags for errors; the S7-1200 has structured diagnostic information accessible via the GET_DIAG system FB.
  7. Burn-in. Run the converted program under normal load for at least 24 hours with logging enabled. Use the TIA Portal trace feature to capture OB1 execution time, cyclic OB jitter, and any non-fatal diagnostic events.

Common Pitfalls and Troubleshooting Matrix

Table 5 — Field-observed conversion pitfalls
Symptom Likely cause Resolution
Outputs latch on after first scan SMB0.1 (first-scan) bit behaviour lost in translation Add OB100 with all outputs forced to a safe state; clear "DB_Migrated".firstScan in OB100
Timer duration is shorter than expected S7-200 timer base (10 ms / 100 ms) not migrated to 1 ms base Re-scale TP / TON PT input by the original time-base factor
HSC count is half the real value Micro/WIN HSC counted edges, S7-1200 counts on configuration-defined edge Check the "Count mode" in the HSC technology object; align with the legacy wiring
Modbus slave does not respond Modbus_Master_P2P using the wrong function code or starting address offset Function code 3 vs 4: confirm whether the slave exposes input or holding registers; reset the offset to 0 if the legacy code expected 1-based
Drive trips on USS comm loss USS_Port_Scan call interval too long Reduce the scan interval to 20..50 ms; check the timeout multiplier on the drive (P2040..P2044 on SINAMICS)
HMI tag shows ### Optimised DB access blocks are not visible from the HMI connection Switch the affected DB to standard (non-optimised) access, or define the HMI-relevant tags in the PLC tag table instead
PROFINET device fails to come up CPU firmware too old for the device GSD Update the CPU to V4.4 (S7-1200) or V1.8 (S7-1500); install the latest HSP for TIA V13
Compile error: address overlaps V-memory addresses were re-declared as overlapping INT/DINT/REAL tags Reorder the DB members so no two tags share a byte boundary, or split into separate DBs
OB82 not triggered on I/O fault Diagnostic interrupt not enabled in device configuration Open the module > Properties > Diagnostics > enable "Hardware interrupt on diagnosis"

Field-Commissioning Checklist

Before the production cut-over, run the following checklist with the responsible engineer signing each line:

  • ☐ All Micro/WIN subroutines have a matching FC or FB in the TIA project.
  • ☐ All Micro/WIN interrupt routines have a matching OB (cyclic, HW interrupt, or time-of-day).
  • ☐ The global tag table contains a typed counterpart for every V-memory reference used by the legacy program.
  • ☐ No raw SMB or SMW references remain in the TIA program.
  • ☐ Serial communication has been re-verified with a Modbus scanner or USS trace.
  • ☐ PTO/PWM outputs have been observed on an oscilloscope, not just the watch table.
  • ☐ PID loops have been auto-tuned with the actual process connected.
  • ☐ HMI faceplates point at DB tags, not Merker addresses.
  • ☐ Diagnostic OBs (OB82, OB85, OB121, OB122) contain a logging call so future faults are visible.
  • ☐ The project backup (.ap13) has been archived to the engineering vault with a dated revision tag.

FAQ

Is there a Siemens tool that converts STEP 7 Micro/WIN projects to TIA Portal V13 directly?

No. The legacy Micro/WIN-to-TIA conversion add-on shipped with TIA V10 / V11 has been discontinued, and TIA V13 has no built-in importer for .mwp files. Manual re-authoring of the logic in TIA Portal V13 is the recommended path; use the printed Micro/WIN project as the functional specification.

Which S7-1200 CPU should replace an S7-200 CPU 226 in a typical mid-size machine?

An S7-1200 CPU 1215C DC/DC/DC (6ES7215-1AG40-0XB0) is the closest functional match for an S7-200 CPU 226 (6ES7210-2BD23-0XB0). It offers two PROFINET ports, 24 V DC supply, and onboard analog I/O. For applications that need faster scan or larger memory, step up to the S7-1500 CPU 1511-1 PN (6ES7511-1AK02-0AB0).

How do I migrate an S7-200 Freeport program that uses XMT and RCV with an interrupt routine?

Replace XMT with the Send_P2P FB and RCV with the Receive_P2P FB from the TIA V13 PtPCom library on a CM 1241 (RS-232 / RS-485) or CB 1241 (RS-485) module. Map the S7-200 SMB30/SMB130 port-control bits to the CM 1241 port configuration, and re-implement the receive-complete interrupt as an OB40 hardware interrupt on the configured RCV completion event.

Can I keep the S7-200 PPI network cabling when I migrate to S7-1200?

PPI is an S7-200-only protocol. The S7-1200 cannot speak PPI, so the cable plant must be replaced with PROFINET or PROFIBUS DP. If you must preserve an RS-485 multi-drop bus, the S7-1200 can act as a Modbus RTU master via CM 1241; re-author the legacy master code accordingly.

What happens to the S7-200 SM bits like SM0.0 (always-on) and SM0.5 (1 Hz clock) in TIA Portal?

SM bits have no equivalent in TIA Portal. Recreate SM0.0 with a tag that is unconditionally TRUE in OB1, recreate SM0.1 with a one-shot set in OB100 (warm restart), and replace SM0.5 with a clock-bit generator implemented as a 1 Hz toggle on a cyclic OB30 or use the CPU clock memory byte configured under CPU properties > System and clock memory.

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