Migrating Siemens S7-400H 417-4H to 417-5H CPU (4HL to 5HT06)

1. Overview: S7-400H Redundant CPU Upgrades

The SIMATIC S7-400H is Siemens' high-availability, fault-tolerant PLC platform. The "H" suffix denotes redundant operation: two identical CPUs run synchronously, exchange process state through fiber-optic sync modules, and take over each other's load if a fault is detected. The platform supports online repair and component replacement without stopping the process, but only when the change rules in the S7-400H Fault-Tolerant Systems manual are followed.

This reference addresses two upgrade paths commonly raised by integrators and plant engineers:

• Path A — 6ES7 417-4HL00-0AB0 or 6ES7 417-4HL01-0AB0 → 6ES7 417-4HL04-0AB0 (in-frame, re-using the existing backplane and I/O).
• Path B — 6ES7 417-4HL04-0AB0 → 6ES7 417-5HT06-0AB0 (CPU 417-4H generation 4 → CPU 417-5H generation 5, V6.x firmware).

Both paths keep the user program in STEP 7, but Path B crosses a major firmware generation boundary (V4.x → V6.x). That boundary introduces behavior changes that must be reviewed against the running program before the new CPU is inserted.

2. Order Number Decoding and CPU Identification

Siemens encodes the CPU family, generation, firmware version, and hardware revision in the MLFB (order number). Decoding the strings in the source:

3. Hardware Comparison: 417-4H vs 417-5H

4. Firmware Generation Differences (V4.x → V6.x)

Path B is a firmware-generation upgrade, not just a memory upgrade. The 5HT06 runs V6.x firmware, and the running user program must be reviewed for behavior deltas. Categories of change typically encountered between V4.5 and V6.x:

1. System data blocks (SDB): generated differently. Recompiling the HW Config from STEP 7 V5.5 SPx (or TIA with the matching HSP) produces the new SDB set. Old SDBs are not portable.
2. OB reaction to faults: OB 80, OB 82, OB 83, OB 85, OB 86, OB 87, OB 121, OB 122 priorities and start information were adjusted. Any user code in these OBs must be re-validated.
3. Self-test diagnostics: extended self-test runs; some previously logged diagnostic events are now classified differently. Diagnostic buffer (OB 100, SZL lists) layout changed.
4. Communication: the S7 communication resource table, connection count limits, and ISO-on-TCP keep-alive behavior changed in V6. Programs that rely on exact timing of PUT/GET/BSEND may need timing adjustments.
5. Time synchronization: handling of SIMATIC Time, NTP, and PROFIBUS time master has been unified. Any time-of-day conversion blocks should be re-tested.

5. Path A: 4HL00 / 4HL01 → 4HL04

This is a same-family, same-form-factor replacement. The 4HL04 is mechanically and electrically compatible with the 4HL00 / 4HL01 slots. The backplane, sync modules, sync cables, and power supply are reused.

5.1 Hardware impact

• Mechanical: none. The 4HL04 occupies the same 2-slot width as the 4HL00/4HL01.
• Electrical: none. Insertion into a UR2/UR2-H or CR3-H rack is identical.
• Sync modules: reuse the existing 6ES7 960-1AA04-0XA0 (or 6ES7 960-1AB04-0XA0) modules. The fiber-optic cables do not need replacement.
• Battery / MMC: the 4HL04 supports the SIMATIC Memory Card. The Flash card from the older CPU can be re-used if the firmware on the card matches the destination; otherwise, a fresh card is required.

5.2 Software impact

• The user program is re-compiled against the V4.5 firmware target. STEP 7 V5.4 SP5 or higher is recommended.
• Hardware Config is re-loaded; the SDBs are regenerated.
• Symbol table, comments, and source structure are preserved.
• Existing PCS 7 libraries and CFC/SFC charts can normally be loaded unchanged if the PCS 7 version is the same or newer.

5.3 Procedure (Path A, in H redundancy)

1. Document the current diagnostic buffer of both CPUs (online → CPU → Diagnostic buffer).
2. Download a backup of the project from the running H station.
3. Switch the master CPU to STOP-RUN with the standby CPU in RUN (H system tolerates single-CPU redundancy briefly). Confirm the standby is in RUN and synchronized.
4. Pull the master CPU (4HL00 or 4HL01). H system continues in single-CPU mode.
5. Insert the 4HL04 in the same slot. Wire the sync cable into the new sync modules if pre-wired; otherwise reuse existing modules.
6. Insert the Flash card. Power up the new CPU.
7. Download the project to the new CPU. The CPU performs link-up and establishes redundancy.
8. Verify H status: LED RACK 0 and IFM on the sync modules; both CPUs reach RUN-H.
9. Repeat steps 3–8 for the second CPU once the system has stabilized for the documented dwell time (typically 10–15 minutes of clean redundancy).

6. Path B: 4HL04 → 5HT06

This is a CPU-generation upgrade. Although the 417-5H is mechanically compatible with the 417-4H slot footprint, the V6.x firmware and the new system data set require careful preparation. The single biggest risk is bringing a 5HT06 into a redundancy pair that still contains a 4HL04: an H pair with mixed generations does not enter RUN-H. The mixed pair must be operated in single-CPU mode until both CPUs have been replaced.

6.1 Hardware impact

• Mechanical: identical form factor; no rack or wiring changes.
• Power consumption: marginally higher. If the existing PS 405/PS 407 is loaded above 70% of its rated current, recalculate with the new figure. The 5HT06 is in the same bracket as the 4HL04, so a well-sized supply typically does not need replacement.
• Sync modules and cables: reuse existing 6ES7 960-1Ax04-0XA0 modules. The 5HT06 supports the same fiber-optic sync interface.
• Memory cards: the 5HT06 requires a Flash card with the matching V6.x firmware image. The card from a 4HL04 cannot be read by the 5HT06 because of the firmware change. Order the Flash card pre-imaged or use a separate programming device to load the firmware image before insertion.

6.2 Software impact

• Project must be migrated to STEP 7 V5.5 SPx (or to TIA Portal with the appropriate H-System Package). V5.4 cannot generate SDBs for the 5HT06.
• HW Config must be re-built with the 417-5H as the target. Slot numbering, module selection, and PROFIBUS addresses are preserved.
• All blocks must be re-compiled; the compilation flags for V6 are different.
• All OB fault-handling code must be re-validated against the V6 startup information.
• CFC/SFC charts from PCS 7 V7.1 SPx or higher can normally be carried over if the underlying CPU target is updated. Older PCS 7 charts must be migrated to the matching PCS 7 release before download.

6.3 Mixed-pair behavior

Because of this restriction, the second CPU must be replaced in a planned outage window or during a temporary period of single-CPU operation.

7. Programming / Software Migration Procedure (Path B)

1. Open the project in STEP 7 V5.5 SPx (or later). Do not open the same project in two different STEP 7 versions.
2. In HW Config, replace the CPU 417-4H order number with the 417-5H (6ES7 417-5HT06-0AB0). Keep slot, sub-module, and addressing unchanged.
3. Compile and save HW Config. The compiler regenerates the system data blocks (SDBs).
4. Re-compile the entire user program: Program blocks → right-click → Compile All. Resolve any redefinition warnings that appear.
5. Re-compile CFC/SFC charts if PCS 7 is in use: Chart → Compile → Chart → Save As.
6. Run a consistency check: Options → Check Block Consistency and Options → Cross References to flag any unresolved symbols.
7. Perform a program download dry run on the engineering station to confirm the block sizes fit in the new work memory limits.
8. Save the project under a new name (e.g., plant_xy_417-5H_V6.mcp) and archive the previous project.

8. Hot-Swap Procedure for Both CPUs in Path B

1. Preconditions:
   • Both CPUs (4HL04) are in RUN-H and synchronized.
   • Two replacement 5HT06 CPUs are on site, each with a Flash card loaded with the target firmware.
   • Engineering station has the migrated project loaded and compiled.
   • Plant operator and maintenance are informed; critical interlocks are monitored.
2. Replace CPU 0:
   • CPU 0 is the master (or one of the master pair, depending on assignment). The other CPU takes over automatically when CPU 0 is pulled.
   • Remove CPU 0.
   • Insert the new 5HT06 into slot 0. Insert the pre-loaded Flash card.
   • The new CPU powers up in STOP. Download the migrated project.
   • Switch the new CPU 0 to RUN. The system runs in mixed pair / single-CPU mode: the new 5HT06 is the master, the old 4HL04 is in standby but cannot link up. Process continues on the 5HT06 alone.
3. Replace CPU 1:
   • Plan this step during a maintenance window, or accept a short single-CPU interval.
   • Stop the existing CPU 1 (the 4HL04). The 5HT06 continues as sole master.
   • Pull the 4HL04, insert the second 5HT06 with its Flash card.
   • Download the project to the new CPU 1 and switch it to RUN.
   • The system performs link-up. After the configured redundancy dwell time (default 10 s; check LINK_UP_DELAY parameter in HW Config) both CPUs reach RUN-H.
4. Post-replacement checks:
   • Diagnostic buffer of both CPUs: no new error events.
   • Sync module LEDs: LINK-UP green on both modules of both CPUs.
   • Operator view: H status indicator is green on both racks.
   • Forced test of takeover: on an out-of-service actuator, pull the master CPU and confirm the standby takes over within the configured max-tolerated takeover time (default 100 ms; check MONITOR_TIME in the H parameters).

9. Verification and Commissioning Checklist

10. Risk Matrix and Mitigations

11. Engineering Reference Links

• S7-400H Fault-Tolerant Systems, System Manual (entry point)
• SIMATIC S7-400H CPU 417-5H (6ES7 417-5HT06-0AB0) data sheet
• S7-400H module replacement during operation (section 17.2 reference)
• PCS 7 / S7-400H compatibility list
• STEP 7 V5.5 SPx — Hardware Configuration for S7-400H