Migrating TI 5TI-5500 TMR to Siemens S7 Timer Blocks

David Krause14 min read
HMI ProgrammingSiemensTutorial / How-to
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Overview

The Texas Instruments 5TI-5500 ladder-logic controller (manufactured in the late 1970s and installed through the 1990s) uses a non-IEC timer primitive called TMR with two physical rung inputs: an Enable/Reset coil and a Start coil. This two-input model is unusual compared with the single-input IEC 61131-3 timers used in every modern Siemens S7 CPU (S7-300, S7-400, S7-1200, S7-1500). When porting a 25-year-old 5TI program to STEP 7 (classic) or TIA Portal, the timing logic must be rewritten so the original Enable/Start semantics — including the freeze-on-Start-OFF behavior — are preserved.

This reference documents the exact behavior of the 5TI TMR instruction, maps each input to the closest S7 primitive, and provides drop-in replacement code in LAD, FBD, and SCL for both the retentive on-delay and the retentive off-delay variants. Two implementation paths are covered:

  1. The legacy TI-S7 Converting Blocks library (FC80 TONR, FC81 TOF, FC82 pulse) supplied by Siemens for migration projects.
  2. Native S7 timers (S_ODTS / S_OFFDT for STEP 7 classic, or TP / TON / TOF / TONR for TIA Portal) combined with small logic networks that re-create the dual-input control.

The TIA Portal documentation entry that describes the underlying timer mechanics is the SIMATIC S7-1200 Manual Collection — Timer Operation (IEC Timers) page. Although written for the S7-1200, the IEC timing rules and DB-resident timer structure apply identically to S7-300/400 in STEP 7 classic.

Understanding the TI 5TI-5500 TMR Instruction

The 5TI-5500 TMR is a non-retentive looking but actually conditionally retentive timer. Its truth table is reproduced from the original TI Series 5TI Programming Manual:

Input 1 (Enable / Reset) Input 2 (Start) Behavior Accumulator (ACC) Output (T)
OFF (0) X (don't care) Forced reset 0 0
ON (1) OFF (0) Hold — timing paused, value retained Unchanged Unchanged
ON (1) ON (1) Run — accumulator increments each scan Incrementing Set when ACC ≥ Preset

Three timing points need to be migrated:

  1. The accumulator must freeze the moment Start goes OFF while Enable is still ON.
  2. The accumulator must resume from the frozen value the moment Start returns to ON (no re-load to zero).
  3. The accumulator must be asynchronously cleared the moment Enable goes OFF, regardless of Start.

The 5TI TMR time base is 0.1 s per count, and the preset is a BCD constant loaded from the rung. The S7 equivalent uses a 100 ms time base by default for S7-300/400 timers (S5TIME format S5T#), or milliseconds in TIA Portal (TIME / LTIME format).

S7 Standard Timer Primitives (STEP 7 Classic)

STEP 7 classic exposes five ladder timer boxes plus the underlying IEC blocks. Each box uses a system clock byte from the CPU's internal timer area (default 0.1 s update for the S7-300/400) and stores the current value in the lower 16 bits of word MWx (configurable).

Box Behavior on IN=0 Behavior on IN=1 Reset input Match for 5TI TMR?
S_PULSE Immediate reset Run for PT, ignore further IN transitions None No — pulse, not retentive
S_PEXT Immediate reset Run for PT, retriggered by any rising IN None No — pulse, not on-delay
S_ODT Immediate reset Run for PT, Q follows accumulator None Partial — single input
S_ODTS Hold accumulator and Q Run for PT from held value None Closest native match — see migration section
S_OFFDT Hold accumulator and Q Start off-delay on falling edge of IN None Used for the off-delay variant

Of the five, S_ODTS (Retentive On-Delay Timer) most closely resembles the 5TI TMR with one limitation: it has a single input, not two. The S_ODTS pauses when IN=0 but never resets the accumulator; the only way to clear it is by overwriting the timer word or restarting the CPU. That is not acceptable for control logic, so an external reset is required.

IEC 61131-3 Timer Types in TIA Portal (S7-1200 / S7-1500)

On the S7-1200 and S7-1500, the IEC blocks TP, TON, TOF, and TONR replace the legacy S5 boxes. Each instance stores its state in a system-owned IEC_TIMER / TONR / TOF data block in the work memory, and the CPU services it from a 1 ms high-resolution clock. The general rules apply across the family:

  • TP — pulse, edge-triggered on IN rising. Not retentive.
  • TON — non-retentive on-delay. IN=0 → ET=0, Q=0.
  • TOF — off-delay. IN=0 starts the count down; Q remains TRUE while ET < PT.
  • TONR — retentive on-delay. IN=0 freezes ET; only R=1 clears it.

Per the official TIA Portal documentation (SIMATIC S7-1200 Manual — IEC Timer Operation), the TONR block is the direct behavioral replacement for the 5TI TMR provided an additional logic network gates the IN input with the Enable signal:

5TI TMR input TIA Portal TONR wiring
Enable / Reset (coil 1) INVERT to enable_bar; use enable_bar as the R input of TONR
Start (coil 2) Feed to IN of TONR through an AND with the Enable signal
Preset (BCD constant on rung) Convert to TIME literal, assign to PT of TONR
Output (T) Read Q of TONR

FC80 TONR — The TI-S7 Conversion Library Approach

Siemens published a free library called TI-S7 Converting Blocks on the legacy support site (entry ID 858026) to help customers port TI 5TI and Series 505 programs to STEP 7. The library exposes the original TI instruction set as a set of FBs and FCs that you call from the S7 program. The three timer blocks of interest are:

Block Name Inputs Match to 5TI TMR
FC80 TI_TONR (retentive on-delay) START, RESET, PRESET, TIME_BASE Direct equivalent of 5TI TMR with 0.1 s base
FC81 TI_TOF (off-delay) START, RESET, PRESET, TIME_BASE Off-delay with reset input
FC82 TI_PULSE START, RESET, PRESET, TIME_BASE Pulse generator

To use FC80 in a STEP 7 classic project:

  1. Open the library archive TI-S7_xx.zip in SIMATIC Manager and copy the relevant sources into your S7 program (Blocks container).
  2. Add the symbols you need to the Symbol Table — for example, Motor1_TMR as an FC80 instance (call it as a multi-instance or as a standalone FC).
  3. Call FC80 in OB1 (or the cyclic OB used by the project) with the following parameter list:
CALL  FC80
     START  := "Tag_StartCoil"   // 5TI input 2 (Start)
     RESET  := "Tag_EnableCoil"  // 5TI input 1 (Enable, active low internally)
     PRESET := S5T#10S            // BCD preset 10 seconds from the original
     TIME_BASE := 1               // 0 = 0.1 s, 1 = 1 s, 2 = 1 min
     ET     := MW100              // current elapsed time (WORD)
     RT     := MW102              // remaining time (WORD)
     Q      := "Motor1_RunOK"     // output replaces 5TI T-bit
     BI     := MW104              // BCD display of ET
Note on polarity: FC80 is internally wired for active-high Start and active-high Reset. If you need the 5TI convention where Enable=OFF forces a reset, drive the FC80 RESET input with the inverse of the Enable coil using a NO contact of NOT Enable in ladder, or use a separate NC contact in series with the Start rung.

The benefit of the conversion-library approach is byte-for-byte preservation of the 5TI logic — the rung-by-rung functional behavior, including the freeze-on-Start-OFF characteristic, is reproduced without any additional glue logic. The drawback is the library was last updated in the early 2000s and does not have TIA Portal versions; on S7-1200/1500 you must either import the FC80 source as a non-optimized FB and remap its parameters to symbolic tags, or recreate the logic with native TONR as shown in the next section.

Custom Ladder Implementation for Two-Input Retentive Timer

When the conversion library is unavailable — for example on S7-1500 with optimized block access, or on S7-1200 with TIA Portal V15+ — re-create the 5TI TMR with a TONR plus a small ladder network. The complete LAD network that emulates the 5TI TMR is shown below.

Network 1 — Enable / Reset gating

       Enable  Start                "TMR_Internal_IN"
  ───┤ ├──────┤ ├──┬────────────────────────────────( )───┐
                    │  (TMR_Internal_IN = Enable AND Start) │
                    │                                          │
       /Enable      │                                          │
  ───┤/├────────────┘                                          │
                                                                 │
   ┌──────────────────────────────────────────────────────┐    │
   │  CALL  TONR_DB                                        │    │
   │     IN     := "TMR_Internal_IN"                       │    │
   │     PT     := T#10s                                   │    │
   │     R      := "/Enable"                               │    │
   │     ET     := "TMR_ET"                                │    │
   │     Q      := "TMR_Q"                                 │    │
   └──────────────────────────────────────────────────────┘    │
                                                                 │
   Output coil:
  ───┤ TMR_Q ├──────────────────────────────────────────────( )─

Network 1 in Structured Text (SCL)

// 5TI TMR emulation in SCL
IF NOT "Tag_EnableCoil" THEN
    // 5TI rule: Enable OFF = forced reset
    "TMR_Internal_IN" := FALSE;
    "TMR_DB".R := TRUE;          // edge-reset on the TONR
    "TMR_DB".IN := FALSE;
    "TMR_DB".PT := T#10s;        // preset carried over from 5TI rung
ELSE
    "TMR_DB".R := FALSE;
    "TMR_Internal_IN" := "Tag_StartCoil";
    "TMR_DB".IN := "TMR_Internal_IN";
END_IF;
"TMR_ET"  := "TMR_DB".ET;
"TMR_Q"   := "TMR_DB".Q;

Behavior verification against the 5TI table:

Enable Start TMR_Internal_IN R TONR accumulator Result vs. 5TI TMR
0 0 0 1 Cleared to 0 ✔ Matches
0 1 0 1 Cleared to 0 ✔ Matches
1 0 0 0 Holds last ET ✔ Matches freeze behavior
1 1 1 0 Accumulates ✔ Matches run behavior

Timing Diagram — 5TI TMR vs. S7 TONR Migration

The SVG below shows the same sequence of inputs on the original 5TI TMR and on the S7 TONR migration rung. The accumulator and Q traces are identical, confirming behavioral equivalence.

EnableStartET (5TI)ET (TONR)Q output Enable=1Start pulseStart pulseStart holdPreset reached

Off-Delay Equivalent (Retentive TOF with Enable/Reset)

Where the 5TI program also used a true off-delay (timer that continues timing after the input drops), the S7 native S_OFFDT box or the IEC TOF block is the closest match. Apply the same Enable/Reset gating rule:

        Enable  Start       "Tof_IN"
  ─────┤ ├────┤ ├─────( )─────────────────────────────────
                │
        /Enable │
  ─────┤/├──────┘
                │
   ┌────────────┴──────────────────────────────────┐
   │  CALL  TOF_DB                                 │
   │     IN  := "Tof_IN"                            │
   │     PT  := T#5s                                │
   │     R   := "/Enable"                           │
   │     ET  := "Tof_ET"                            │
   │     Q   := "Tof_Q"                             │
   └────────────────────────────────────────────────┘

Use the TOF block in preference to off-delay rungs built around TONR, because TOF holds the Q output TRUE while the accumulator counts up after IN goes FALSE, which is the off-delay semantic; building the same behavior with a TONR requires additional state and is more error-prone.

Migration Procedure

  1. Inventory the 5TI program. List every TMR instruction, its preset in tenths of a second, its address, and the two upstream coil addresses.
  2. Decide the target platform.
    • STEP 7 classic (S7-300 / S7-400): use FC80 from the TI-S7 library if available, otherwise S_ODTS with an external reset.
    • TIA Portal (S7-1200 / S7-1500): use TONR plus the gating network above. The conversion library is not ported to TIA Portal.
  3. Allocate timer DBs. In STEP 7 classic, an FC80 call uses the global memory words (ET, RT, BI) declared at the call site. In TIA Portal, each TONR / TOF instance is its own IEC_TIMER / TOF data block; multi-instance placement inside a parent FB keeps the symbol table compact.
  4. Convert the preset. A 5TI BCD preset of 100 equals 10.0 s. In STEP 7 classic: S5T#10S. In TIA Portal: T#10s or TIME#10s. The time base is implicit in the IEC type and is millisecond resolution on S7-1200/1500.
  5. Wire the Enable / Reset polarity. Use an NC contact (|/|) of the Enable coil in series with the R input of TONR, or a NO contact in series with the Start contact feeding IN. Confirm the polarity against the 5TI truth table.
  6. Replace the T-bit output with the Q output of the new block. If the original rung branched on the T contact downstream, map each T contact to the new Q tag.
  7. Retain the BCD display (optional) by using the BI/BCD output of FC80 in STEP 7 classic, or by formatting ET with DINT_TO_BCD in TIA Portal for HMI display.
  8. Compile and download the S7 program. In TIA Portal, check the Cross References view to ensure every legacy TMR address has a corresponding new instance and no unused tags remain.

Verification and Commissioning Tests

Commission the new program with the same four-step test sequence used to verify the original 5TI logic. Add Online & Diagnostics watch tables to the IEC timer tags so you can observe ET and Q live.

  1. Reset test. Force Enable=0 for 5 s. Confirm ET = 0 and Q = 0 regardless of Start.
  2. Hold test. Force Enable=1, Start=0. Confirm ET holds the last value for 30 s without drift.
  3. Run test. Force Enable=1, Start=1. Confirm ET increments at the configured time base and Q transitions to 1 when ET ≥ PT.
  4. Retentive resume test. Force Enable=1, Start=1 for half the preset, then Start=0 for 10 s, then Start=1 again. Confirm ET resumes from the held value (does not restart from zero) and Q transitions to 1 after the cumulative time reaches PT.

For STEP 7 classic, use the VAT (Variable Table) editor; for TIA Portal, use a Watch Table with the Monitor all toggle. Document the observed values in the project commissioning report.

Troubleshooting Matrix

Symptom Likely cause Resolution
ET counts even when Enable=0 R input of TONR is wired active-high, but 5TI convention is Enable=0 → reset Invert Enable with NC contact, drive R input; recompile
ET resets every time Start drops Using TON instead of TONR Change block to TONR; verify IEC_TIMER instance in TIA Portal
Q never goes TRUE Preset is 0 after BCD conversion, or PT format is wrong (S5TIME vs. TIME) Re-enter preset; for STEP 7 classic use S5T# format, for TIA Portal use T#
ET increments 10× too fast or 10× too slow Time base mismatch (5TI is 0.1 s per count) For FC80, set TIME_BASE parameter to 0 (0.1 s); for native TONR, scale the preset by 100
FC80 call returns SF (system fault) on S7-1500 Legacy library does not support optimized block access Open FC80 properties → Attributes → uncheck "Optimized block access", recompile
Timer tags flicker in HMI HMI is polling ET at 1 s while timer updates at 100 ms Increase HMI acquisition cycle to 100 ms or 200 ms; alternatively, display Q only and use ET in engineering view

Performance and Sizing Notes

The 5TI-5500 scanned its program in a single-pass manner at a fixed cycle of about 5 ms per 1 K of ladder. S7-300/400 with OB1 runs at 10–50 ms typical, S7-1500 with OB1 at 1–10 ms. The retentive timer migration is timing-agnostic at the application level (the ET value is correct regardless of cycle time) but the accuracy of the Q output transition equals one OB1 cycle. If the original 5TI rung relied on a 50 ms preset, test the new rung under the same I/O load to confirm the S7 cycle is not larger than the preset.

For each migrated timer, allocate the following memory in STEP 7 classic (16 bytes total) or in a single IEC_TIMER DB in TIA Portal (16 bytes including the two-word ET, status, and reserved area):

Block type Memory footprint Multi-instance recommendation
FC80 standalone (STEP 7 classic) 12 bytes + global MW Use multi-instance inside a project FB if you have more than 20 timers
S_ODTS native 16 bytes (2 words) Use system clock byte 0 (default)
IEC TONR (TIA Portal) 16 bytes per IEC_TIMER DB Always place inside a parent FB as multi-instance to keep the program blocks tidy

Differences Between FC80 and Native TONR for Migration

Aspect FC80 (TI-S7 library) Native TONR (TIA Portal)
Time base Selectable: 0.1 s / 1 s / 1 min Millisecond, derived from PT format
Reset input Active high RESET Active high R; must be driven by inverted Enable
Retentive across CPU restart No (timer word in MW area) Yes if instance DB is retentive
BCD display (BI/BCD) Yes (BI word) No — must be derived with DINT_TO_BCD
Compatible with S7-1500 optimized blocks No — must be non-optimized Yes
Original 5TI parity 100% 100% with the gating network above

What is FC80 in the TI-S7 conversion library?

FC80 is the retentive on-delay timer block (TI_TONR) supplied in the legacy Siemens TI-S7 Converting Blocks library. It accepts Start, Reset, Preset (in S5TIME), and a Time Base selector (0.1 s, 1 s, 1 min) and returns elapsed time, remaining time, BCD display, Q output, and a binary elapsed-time word. It reproduces the 5TI TMR behavior exactly, including the freeze-on-Start-OFF characteristic.

Can I use the standard S7 TONR instruction to replace a 5TI TMR directly?

Yes, on S7-1200, S7-1500, and S7-300/400 in TIA Portal. Wire the 5TI Start coil to TONR.IN through an AND with the Enable coil, and wire the inverted Enable coil to TONR.R. The internal accumulator will then freeze when Start goes OFF and only clear when Enable goes OFF, matching the 5TI TMR truth table.

How do I implement a retentive off-delay timer in S7 with the same Enable/Reset semantics as the 5TI TMR?

Use the IEC TOF block (S7-1200/1500) or the S_OFFDT box (STEP 7 classic). Drive TOF.IN with the AND of the Enable and Start signals, drive TOF.R with the inverted Enable signal, and read TOF.Q for the output. The TOF output remains TRUE while ET is counting up after IN transitions to FALSE, giving the off-delay semantic with the same dual-input control surface as the 5TI program.

What is the difference between S_ODTS and S_OFFDT in STEP 7 classic?

S_ODTS is a retentive on-delay: Q goes TRUE after IN has been TRUE for PT seconds and remains TRUE even if IN drops. S_OFFDT is an off-delay: Q goes FALSE after IN has been FALSE for PT seconds, with Q following IN up to the start of the count-down. For the 5TI TMR, S_ODTS is the closer on-delay match; S_OFFDT is used when the original rung was a true off-delay.

How do I preserve the 5TI retentive timer value across a CPU restart on S7-1500?

In TIA Portal, open the IEC_TIMER instance DB that backs the TONR, switch to Retain in the properties, and tick the ET and status fields. The accumulator and output state are then backed up in the CPU's retentive memory area and recovered automatically on the next OB1 startup.

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