Mitsubishi FX1N Encoder Resolution: Quadrature Decoding Methods and Hardware Limits

Positioning accuracy on a Mitsubishi FX1N PLC is constrained by the resolution of the incremental encoder feeding its high-speed counters. Engineers commissioning conveyors, cut-to-length systems, and rotary indexing stations frequently discover that 256 pulses per revolution (PPR) at a 1.36 pulses-per-mm linear scale is not fine enough for their application. This reference explains the math behind quadrature decoding, what the FX1N hardware can and cannot do natively with counter C251, how to implement software x4 decoding with input interrupts, and when an external clock/direction converter or a higher-resolution encoder is the correct field-proven solution.

1. Encoder Resolution Fundamentals

An incremental encoder produces two square-wave channels, A and B, mechanically offset by 90 electrical degrees. The fundamental metric published on every encoder datasheet is pulses per revolution (PPR), which equals the number of complete A-B cycles per shaft revolution. Each cycle contains four logic transitions (A↑, B↑, A↓, B↓), which is the basis of quadrature multiplication.

A 256 PPR encoder therefore generates 256 complete A-B cycles per revolution. The physical line count is fixed; only the way the receiver interprets the four edges per cycle can change the effective count. The general rule is:

Effective resolution (counts/rev) = PPR × multiplication factor

where the multiplication factor is 1 (x1, single edge), 2 (x2, both edges of A), or 4 (x4, all four transitions).

2. Quadrature Decoding Theory: x1, x2, and x4

Quadrature decoding exploits the 90° phase shift between channels A and B. A clockwise rotation sequence looks like 00 → 10 → 11 → 01; counter-clockwise produces the reverse: 00 → 01 → 11 → 10. A receiver that latches every transition knows both the magnitude (one count per transition) and the sign of motion.

The state machine for x4 decoding is a 4-bit Gray-code transition table. Each entry of the table is indexed by the current (A,B) state and contains the count delta (+1 or -1) and the next legal state. A noise-tolerant implementation includes a hysteresis filter so a brief glitch cannot generate a phantom count.

3. Mitsubishi FX1N High-Speed Counter Architecture

The FX1N family provides hardware high-speed counters C235 through C255. These counters are serviced by dedicated hardware and can register edges far faster than the scan cycle. Their assignment is fixed: each counter is wired to a specific subset of inputs X0–X7 and supports a defined counting mode.

4. C251 Behavior: Why Resolution Does Not Quadruple

Counter C251 is the standard choice for an AB-phase encoder on the FX1N. According to the FX1N Programming Manual, C251 is described as "1-phase 2-input counter (A/B phase)" and is incremented/decremented by hardware based on the phase relationship. Mitsubishi's documentation explicitly identifies the mode as AB phase mode, which increments/decrements on the leading edge of A while B determines the direction.

Concretely: C251 counts the leading edge of A only, not the trailing edge. The result for a 256 PPR encoder is:

C251 counts per revolution = 256 (one count per cycle, not 1024)

This is the well-documented source of confusion cited in the original query. The user observed 1.36 pulses per mm at 1:1 gearing; with C251 alone, the application cannot exceed 256 counts per shaft revolution. The PLC's hardware does not perform x4 multiplication on C251.

To obtain higher effective resolution, the user must either:

1. Implement a software x2 or x4 decoder using FX1N input interrupts.
2. Add an external quadrature-to-clock/direction converter module between encoder and PLC.
3. Replace the encoder with a 1024 PPR (or higher) device so that C251 alone provides the desired count.

5. Software Quadrature via FX1N Interrupts

The FX1N supports input-edge interrupts. Each input can be assigned one rising-edge pointer and one falling-edge pointer:

• I001 = rising edge on X0, I100 = falling edge on X0
• I101 = rising edge on X1, I101 is actually a fall on X1; correct label is I000/I100 for X0, I001/I101 for X1, and so on

For a 4× decoder the program needs to react to all four edges of A and B. Because each physical input can carry only one interrupt pointer in each direction, the encoder channels A and B must be wired to four separate FX1N inputs:

Each interrupt service routine (ISR) inspects the current state of A and B and increments or decrements a software counter in the data register area (for example, D0). The skeleton of the x4 state machine is shown below.

5.1 Example Ladder for Software x4 Decoder

// --- Main sequence: enable interrupts and start HSC ---
LD    M8000           // RUN contact
FEND

// --- ISR I000: X0 rising edge (A up) ---
I000
LD    X0              // current A state
AND   X1              // current B state (in-phase: up-count)
INC   D0
IRET

// --- ISR I100: X2 falling edge (A down) ---
I100
LD    X0
ANI    X1             // B low: down-count
DEC   D0
IRET

// --- ISR I001: X4 rising edge (B up) ---
I001
LD    X1
AND   X0
INC   D0
IRET

// --- ISR I101: X3 falling edge (B down) ---
I101
LD    X1
ANI    X0
DEC   D0
IRET

The principle is correct, but the practical question is: can the FX1N reliably service four software interrupts at the rate the encoder delivers edges?

5.2 Realistic Bandwidth of the Software x4 Decoder

Independent bench tests of FX-family interrupt-driven quadrature have measured reliable operation only up to roughly 0.5 revolutions per second on a 200 PPR encoder. Above that frequency the ISR latency exceeds the inter-edge interval, and the program begins to lose edges or — worse — produce erratic direction counts. The cause is that the FX1N ISR dispatch is not deterministic: it is interleaved with the scan and is influenced by active peripheral instructions, communication refresh, and the priority of the instruction that was executing when the edge arrived.

6. Hardware Clock/Direction Converter Approach

A more robust solution is to insert a dedicated encoder interface module between the encoder and the FX1N. These modules accept the two quadrature channels A and B and emit a clock/direction pair:

• Clock output: a one-shot pulse at each of the four quadrature transitions.
• Direction output: a static high/low level indicating CW or CCW at the moment of the clock pulse.

The PLC then increments or decrements a high-speed counter based on the clock pulses and the direction level. This converts the four-edges-per-cycle problem into a single-edge count with an additional logic input, which the FX1N HSC can handle.

Encoder manufacturers offer such devices in their accessories catalogs. Industrial converter modules from Kübler, Hengstler, Pepperl+Fuchs, and others are common in the field. Select a converter that supports your encoder's output type (push-pull, line driver RS-422, or open-collector HTL) and your supply voltage (commonly 5 V TTL or 24 V HTL).

7. Resolution Comparison Table

The three practical approaches for a 256 PPR encoder feeding an FX1N produce different effective counts per shaft revolution. The table assumes no gearing between encoder and driven axis.

8. Practical Limits and Field Considerations

8.1 Mechanical and Electrical Constraints

• Shaft speed and frequency: A 256 PPR encoder spinning at 3000 rpm produces 256 × 50 = 12,800 cycles per second, or 51,200 edges per second. This exceeds the C251 30 kHz rating. For the application to work at all, either the shaft must be slow enough or a divider must be applied.
• Voltage compatibility: Most FX1N inputs are 24 V DC sinking. Encoders with 5 V TTL line driver outputs require a signal-level translator before they can be wired directly to the FX1N.
• Cable length and noise: Long encoder cables pick up noise that creates phantom edges. Shielded twisted pair with the shield grounded at the panel end is mandatory; use differential (RS-422) output encoders when cable runs exceed 10 m.

8.2 Counting Arithmetic

For the application described — a conveyor driven at 1.36 pulses per mm using a 256 PPR encoder — the conversion to linear distance is:

Distance (mm) = counts / (PPR × 4) × mm per revolution

If the encoder is on the conveyor drive shaft and the wheel diameter D (mm) defines the linear travel:

mm per revolution = π × D

At 1.36 pulses per mm, the mm/rev is 1 / 1.36 × PPR = 188.2 mm. The implied wheel circumference is therefore about 188 mm, which corresponds to a 60 mm diameter drive wheel (π × 60 = 188.5). With x4 decoding the linear resolution becomes 0.184 mm per count, sufficient for most cut-to-length accuracy requirements below ±0.5 mm.

8.3 Scan-Time and HSC Behavior

The FX1N's high-speed counters are updated independently of the scan, so the value latched into the counter register is always current at the time the CPU reads it. This means that any of the methods above (C251, software x4, or external converter) can be polled by a normal ladder contact without losing counts — provided the program does not miss interrupts, which is precisely the failure mode of the software x4 approach at high frequency.

9. Recommended Encoder Upgrade Path

For most production scenarios, the cleanest engineering answer is to replace the 256 PPR encoder with a 1024 PPR (or higher) device and let C251 handle the count directly. The mechanical envelope of most incremental encoders is standardized, so a swap is usually a drop-in change.

1. Identify the encoder form factor (shaft diameter, flange, cable exit).
2. Match the electrical interface (push-pull 24 V, open-collector, or 5 V line driver).
3. Select a PPR equal to 4× the current encoder (1024 PPR for a 256 PPR swap).
4. Update the program constants: mm per count = 1 / (1.36 × 4) = 0.184 mm.
5. Validate maximum counting frequency against shaft speed: f_max = PPR × RPM / 60 must remain below 30 kHz for C251.

For a 1024 PPR encoder at 1800 rpm, f_max = 1024 × 1800 / 60 = 30,720 Hz, which is right at the C251 limit. Below 1750 rpm the system runs comfortably; above it, the HSC will start missing counts silently. The application must therefore respect the speed-resolution product.

10. Baumer MDFK 08G2101 Specifics

The encoder in the original application is identified as a Baumer MDFK 08G2101, a magnetic incremental encoder with a 32-pole ring magnet. Magnetic encoders of this family provide a base resolution related to the pole count and then apply internal interpolation to reach the catalog PPR value. The 32-pole magnetic ring yields 8 magnetic cycles per revolution; internal interpolation is used to reach the published PPR.

Verify the published PPR of the specific G2101 variant against the application requirement. Magnetic encoders are sensitive to installation tolerances — radial runout, axial play, and air gap all affect the output waveform integrity, which in turn affects the achievable x4 resolution at the PLC. Confirm the operating air gap and shaft concentricity with the Baumer installation guide for the MDFK 08 family before relying on the datasheet PPR value.

11. Step-by-Step: Commissioning the Software x4 Decoder (Reference Only)

The following procedure documents the interrupt-based approach for engineers who must deploy it on existing hardware. It is offered for completeness, not as a recommended production solution.

1. Wire the encoder: A→X0, B→X1. Mirror the channels onto X2 and X3 (or X4, X5) using a passive splitter so all four edges are available on separate inputs.
2. Assign interrupt pointers: I000 (X0↑), I100 (X2↓), I001 (X4↑), I101 (X3↓).
3. Insert EI in the main sequence to enable interrupts.
4. Write the four ISRs as shown in section 5.1, with debounce/dither filtering on internal relays.
5. Use D0 as the position accumulator. Replace any DHSCR D161 C251 Y1 reference with the equivalent DHSCR D161 D0 Y1 for the conveyor command.
6. Validate the count under controlled motion: rotate the encoder shaft at a known speed and confirm the count rate matches PPR × 4 × (RPM / 60) with zero lost counts over a 10-revolution test.
7. If the count drifts at higher speeds, abandon the approach and switch to the clock/direction converter.

12. Verification Checklist

13. Frequently Asked Questions