Overview
The Omron CJ2 series is the second-generation successor to the CJ1 modular PLC platform, retaining the CJ1 backplane mechanics while adding a built-in EtherNet/IP scanner, faster instruction execution, expanded memory map, and refined programming environment support. Released in 2009 as an evolutionary expansion of the CJ1 line, the CJ2 does not replace the CJ1 platform; both families remain installable in the same engineering ecosystem for an extended overlap period. The headline change in CJ2 is native EtherNet/IP connectivity on selected CPU models, eliminating the requirement for an external CJ1W-EIP21 communication unit in many topologies.
This reference applies to engineering teams that already operate CJ1 installations, system integrators evaluating migration paths, and OEMs designing new machines that need deterministic Ethernet messaging alongside the established Omron instruction set.
CJ2 Product Line Architecture
The CJ2 family is split into two branches distinguished by processing power and instruction set coverage:
| Branch | CPU Model Group | Position | Key Differentiator |
|---|---|---|---|
| CJ2H | CJ2H-CPU64/65/66/68(-EIP) | High-end | Highest program capacity, full instruction set including advanced function blocks |
| CJ2M | CJ2M-CPU11/12/13/14/15 | Mid-range | Compact, lower-cost, optional built-in I/O on CPU unit |
Both branches share the same CJ-series backplane, the same I/O unit catalog (CJ1W basic and high-density units), the same expansion rack rules, and the same peripheral bus behavior. The choice between branches is driven by program memory ceiling, scan-time requirements, and the need for built-in EtherNet/IP.
CJ2H vs CJ2M CPU Specifications
The table below captures the principal CPU specifications documented for the CJ2 line at announcement. Verify exact program/step capacity in the hardware user's manual (W472) before committing to a build, because Omron periodically issued capacity revisions for high-end CPU68 variants.
| Parameter | CJ2H-CPU6_-EIP | CJ2M-CPU1_ |
|---|---|---|
| Program capacity (steps) | 20K to 400K (CPU-dependent) | 5K to 60K |
| DM area (words) | 32K to 832K | 4K to 64K |
| EM area (banks) | Up to 13 banks (E0_ to EC_) | Up to 4 banks |
| Basic instruction execution | 16 ns | 40 ns |
| MOV/SFB execution | 120 ns typical | 220 ns typical |
| I/O points (CPU + expansion) | Up to 2,560 | Up to 2,560 |
| Built-in EtherNet/IP port | Yes on -EIP suffix models | Optional via CJ1W-EIP21 |
| Built-in serial (RS-232C) | 1 port (Host Link / NT Link / no-protocol) | 1 or 2 ports depending on variant |
| Option board slots | 1 (serial/RS-485) | Up to 2 (serial + I/O option boards) |
| USB programming port | Yes (peripheral USB) | Yes |
| Memory card slot | Yes (CompactFlash on CPU, later SD) | No (project on-board only) |
| Tag memory (symbolic) | Symbolic variable support with CX-Programmer 9.x | Same |
EtherNet/IP Integration
The defining capability of the CJ2 platform is the integration of EtherNet/IP directly onto the CPU chassis, available as a built-in port on -EIP-suffix CJ2H CPUs and achieved externally on CJ2M installations using a CJ1W-EIP21 unit.
Built-in EtherNet/IP on CJ2H-CPU6_-EIP
- Two-port embedded switch (DLR-ready in firmware 2.0+): device-level ring and star topologies are supported without external switches where ring redundancy is required.
- Functions: CIP messaging client/server, I/O connections (originator and target), tag data link with configurable connection counts (typical allowance: up to 32 CIP connections per CPU).
- Maximum cyclic data exchange rate: 1 ms RPI minimum, subject to connection count and CIP path complexity.
- IP configuration: static, BOOTP, or DHCP, configured through CX-Programmer or directly with the rotary switches (last octet override).
CJ1W-EIP21 on CJ2M
When the CJ2M is selected for cost reasons and EtherNet/IP is required, the CJ1W-EIP21 occupies one slot of the CJ1W rack. The connection topology, CIP path, and tag data link configuration are identical to the built-in port model. Two CJ1W-EIP21 units can be installed on a single CPU to provide physically separated subnets (e.g., machine-level vs. plant-level) without additional switches.
EtherNet/IP Commissioning Parameters
| Parameter | Setting Range | Default | Notes |
|---|---|---|---|
| IP address | Any valid IPv4 | 192.168.250.1 (rotary switch default) | Rotary switches ×1 set last octet 0–255 |
| Subnet mask | Class A/B/C valid | 255.255.255.0 | Configurable in CPU DIP / CX-Programmer |
| TCP/UDP port (CIP) | 44818 (standard) | 44818 | Do not change unless isolating from corporate network |
| Multicast TTL (CIP Class 3+) | 1–255 | 1 | Increase for routed CIP traffic |
| Implicit (I/O) connections | 0–32 total per port | 0 | Each connection counts toward connection budget |
CIP Routing and CIP Message Instructions
The standard CIP messaging instructions are available on the CJ2 with the same ladder mnemonics inherited from CJ1: CMND (generic CIP/CPU-bus command), SEND/RECV (network), and MSG (CIP message). The CIP route path syntax follows the convention:
Network,Node,UnitNumber,Port
Example: a CIP message to a PowerFlex drive on EtherNet/IP at IP 192.168.1.50 through the CPU built-in port uses the network byte string 01 00 00 00 C0 A8 01 32 (Ethernet/IP routing prefix + IPv4 address).
CJ1 Backward Compatibility and Migration
One of the central design goals of the CJ2 was to make a migration "additive": existing CJ1 projects must load, simulate, and run on a CJ2 CPU with minimal ladder rework. The compatibility surfaces are explicit:
| Item | Compatible? | Notes |
|---|---|---|
| CJ1W basic I/O units (ID211, OC211, etc.) | Yes | Drop-in, no reconfiguration |
| CJ1W special I/O (AD041, DA041, etc.) | Yes | I/O allocation identical |
| CJ1W CPU bus units (ETN21, EIP21, SCU21) | Yes | Same DM/AR allocation scheme; verify IORF-compatible firmware |
| SYSMAC LINK (SLK21) units | Yes | Routing tables need rebuild on CX-Integrator |
| Existing CX-Programmer 7.x projects | Partially | Auto-convert to CX-Programmer 9.x; review symbol table |
| Existing user programs (.cxp) | Yes with import wizard | S comments and SFC retained |
| Expansion racks (CJ1W-IC101 I/O control, CJ1W-II102 I/O interface) | Yes | Same cable length budget |
Program Conversion Procedure
- Open the existing
.cxpin CX-Programmer 9.x or later. The Convert dialog reports unsupported instructions; address these by verifying no legacy CJ-series libraries were used without an updated FB. - Reallocate I/O tables from the new CPU configuration. CJ2 inherits CJ1 allocations when the rack is physically identical.
- Rebuild any tag-data-link tables if the migration included switching from CJ1W-ETN21 + custom UDP messaging to the native EtherNet/IP port.
- Validate conversion with the Compare tool against the original
.cxp; pay particular attention toPRV(pulse rate) instruction operand formats, which were tightened in CJ2. - Download to a CJ2 CPU and verify each task (cyclic, interrupt) using the Watch Window before fielding the equipment.
Software Environment: CX-Programmer and CX-One
CX-Programmer version 9.0 (or later) is the supported programming IDE for the CJ2 line, typically delivered through the CX-One suite. CX-Programmer 7.x will read a CJ2 project but cannot create one nor will it push a project to the CPU via USB/Ethernet; the editor must be upgraded.
| Software Component | Minimum Version | Required For |
|---|---|---|
| CX-Programmer | 9.0 (initial); 9.6x for advanced tasks | Ladder, ST, SFC, FBD programming |
| CX-Integrator | 2.0+ | Routing tables across CS/CJ EtherNet/IP |
| CX-Simulator | 2.0+ | CJ2 offline debug / hardware-in-the-loop |
| CX-Designer | 3.2+ | NS-series HMI projects interacting with CJ2 tag symbols |
| Network Configurator (part of CX-One) | 3.2+ | CIP tag data link configuration on EtherNet/IP |
Instruction Set Enhancements in CJ2
The CJ2 instruction set is a superset of the CJ1 set. Notable additions include:
- Advanced function blocks ("FB" with structured local variables) for reusable packaging.
- Symbolic variable access from ladder (e.g.,
Motor1_Speedinstead of pure addressD100). - Enhanced
STUP(serial setup) parameters supporting RS-485 multidrop on CPU option board. - Improved string instructions:
MOV$,+$,LEN$,LEFT$,RIGHT$,MID$, with expanded buffer boundaries. - Trigonometric and floating-point extensions:
SIN,COS,TAN,ASIN,ACOS,ATAN,EXP,LOG,POWwith single and double precision operands. - Compact stack-based operations for high-throughput event handling.
Memory Areas (Address Map Summary)
| Area | Symbol | CJ2 Range (typical) | Use |
|---|---|---|---|
| CIO (Core I/O) | CIO | 0–6143 | I/O, CPU bus, serial port status |
| Internal Relays / Work Bits | W | 0–511 | Working bits, internal |
| Holding Relays | H | 0–511 | Retained on power loss |
| Special Relays | A | 0–11535 (CPU- and unit-defined) | Flags and status |
| Temporary / Data Memory | T/C, D | T/C: 0–4095; D: 0–32767 | Timers, counters, general data |
| DM Area | D | 0–32767 (CJ2H: up to 832K with EM) | Data words |
| EM Area (banks) | E0_ ... EC_ | 32K words per bank | Large data, retained across project transfers |
| Index/Indirect | IR, DR | IR0–IR15, DR0–DR15 | Pointer-based addressing |
| Task flags | TK | TK0–TK31 | Task execution indicators |
Hardware Installation Notes
Rack Layout Rules
Three classes of units occupy a CJ2 chassis:
- CPU Unit — slot 0 only.
- CPU Bus Units — CJ1W-ETN21, CJ1W-EIP21, CJ1W-SCU21, etc. Up to 16 per CPU.
- Basic / Special I/O Units — Remaining slots up to rack capacity.
A CPU bus unit's allocation letters and dip-switch position define the DM and CIO ranges used by ladder code; changing slot order between commissioning and field service typically requires re-allocating those areas in the I/O table.
Power and Grounding
- Use CJ1W-PA202 (100–240 VAC) or CJ1W-PD022 (24 VDC) power supply units. The PD022 must be sourced from a regulated, fused 24 VDC rail.
- Ground the CPU via the protective earth (PE) terminal at the power supply; resistance to ground should be 100 Ω or less (Class D grounding for industrial control per local code).
- Maintain separation between analog signal wiring (CJ1W-AD041/DA041) and AC power or VFD power cables; observe 100 mm minimum parallel clearance unless shielded cable is used.
Memory Card Use
The CJ2H supports CompactFlash (later firmware revisions support SD) for project backup and recipe storage. The card must be FAT16-formatted and must not contain files the CPU does not control. Inserting a card with foreign files can stall boot; remove power before insertion and confirm the SLOT indicator on the CPU reads FILE before the program download completes.
CJ2H vs CJ1M/CJ1G Migration Trade-offs
| Aspect | CJ1 (CS1-style legacy) | CJ2 (target) | Migration Cost |
|---|---|---|---|
| Programming software | CX-Programmer 7.x | CX-Programmer 9.x+ | License upgrade |
| EtherNet/IP support | External CJ1W-EIP21 | Built-in or external | Hardware slot savings vs. token cost |
| Memory ceiling | 60K steps typical | 400K steps (CJ2H-CPU68) | Program re-cap |
| Instruction cycle | ~40 ns typical | 16 ns on CJ2H | None — automatic |
| Symbolic variables | Limited (CIO comment) | Full local FB variables | Ladder review |
| Hardware effort | — | Backplane drops in | None / minor rewire if rack re-lays |
Troubleshooting Matrix (EtherNet/IP + Generic CJ2)
| Symptom | Likely Cause | Diagnostic Step | Remedy |
|---|---|---|---|
| CIP connection timeout on first boot | Rotary switches set the wrong last octet or DHCP server unreachable | Read IP from CX-Programmer transfer dialog or with BOOTP viewer | Set static IP or pin rotary switch to match |
| EtherNet/IP connection drops under load | CIP connection count exceeded budget | Check CIP Master / Diagnostics in Network Configurator | Reduce originator count below 32 or split across two EIP ports |
| ERR/ALM LED lit, RUN off | Fatal system fault — see A40115 content | Connect CX-Programmer, read CPU error log | Clear fault per A401 code; cycle power only after recording |
| Program conversion reports "Instruction not supported" | Use of legacy CJ-FB or third-party POUs not in current library | Open unsupported instructions dialog and rebuild | Recreate using CX-Programmer 9.x FB libraries or replace with structured-text equivalents |
| DHCP works but BOOTP fails (or vice versa) | CX-Programmer Transfer dialog setting mismatch | Verify Transfer Settings → Network Type | Set matching method; restart Ethernet port via STUP settings |
| USB transfer not recognized on host | USB driver not installed | Verify Omron CX-Server device in Device Manager | Re-run CX-Programmer install and use the bundled driver; switch to Ethernet if persistent |
| CompactFlash card not detected | Card formatted non-FAT or write-protect enabled | Try a verified industrial-grade CF card (SanDisk or Omron-branded) | Reformat FAT16 on host; verify slot LED pattern |
| Cycle time intermittently exceeds 100 ms | EIP RPI set too aggressive for connection count | Read P_Output_Off_Time and P_Cycle_Time in PLC Status | Raise RPI to 10–50 ms or reduce I/O refresh scope |
Field-Commissioning Checklist
- Confirm chassis and power supply meet the calculated load budget. Sum the CJ1W unit current ratings against the supply's maximum.
- Set the rotary IP-address octet switches to the intended value before applying power.
- Run an I/O verification pass: walk each input and output physically and confirm the corresponding
CIObit transitions in CX-Programmer Watch. - Verify cyclic, interrupt, and (where used) scheduled tasks execute by reading TK00–TK31 flags.
- Connect Network Configurator to the built-in EtherNet/IP port. Open the connection diagnostics and check that the device appears online, that the CIP identity object returns the expected vendor/product codes, and that each originator connection reports "Established."
- Backup the project to the CompactFlash card (CJ2H) and to a protected folder on the engineering laptop before releasing the machine.
- Document the IP addressing, subnet mask, gateway, and connector pin-outs of any RS-232C option board.
Frequently Asked Questions
Does the CJ2 replace the CJ1?
No. The CJ2 was introduced as an evolutionary expansion of the CJ1 chassis, not a forced replacement. Existing CJ1 installations remain supported and CJ1W I/O units fit a CJ2 CPU without modification, leaving system integrators free to choose the new platform on a project-by-project basis.
Which CX-Programmer version supports CJ2 programming?
CX-Programmer version 9.0 or later is required to create or download projects to a CJ2 CPU. Newer revisions such as 9.6x are recommended for stable symbolic addressing, FB development, and CIP messaging diagnostics.
How is EtherNet/IP implemented on the CJ2?
On CJ2H-CPU6_-EIP models the EtherNet/IP port is built into the CPU and provides up to 32 CIP connections, with both CIP Class 3 messaging and implicit I/O connections. On CJ2M CPUs, EtherNet/IP is added through a CJ1W-EIP21 unit installed in a CPU bus slot.
Can a CJ1 program be moved to a CJ2 without rewriting it?
Most ladder, SFC, and function block logic transfers by using the CX-Programmer conversion wizard. Review unsupported-instruction warnings before download, validate the I/O table on the new CPU, and rerun any third-party FBs against the active library version.
What is the difference between CJ2H and CJ2M?
CJ2H is the high-performance branch with up to 400K program steps, built-in EtherNet/IP, and CompactFlash memory-card support. CJ2M is the mid-range branch with lower program capacity but optional built-in I/O on the CPU itself and an optional second serial option board.
What is the maximum CIP RPI achievable on the CJ2 built-in EtherNet/IP port?
The minimum supported Requested Packet Interval (RPI) is 1 ms. Achieving 1 ms in production depends on connection count and ladder cycle time; in practice, 10 ms is the commonly accepted safe RPI for multi-connection installations.