Omron CP1L PC Link Bidirectional RS-422/485 Communication Setup

1. Serial PLC Link (PC Link) Protocol Overview

Omron Serial PLC Link, referred to in the field as PC Link, is a vendor-proprietary data-exchange protocol that runs over an RS-232C or RS-422A/485 channel without any user-written communication Ladder. A CPU configured as Master sequentially polls each Slave in the registered list; every Slave returns the contents of its own 10-word transmission window, and all nodes (Master + Slaves) simultaneously receive the Master's 10-word transmission window. Because both sides of every link run in the same scan, the protocol is intrinsically bidirectional: every node has read-only access to the Master's words and read/write access to its own 10-word window.

The reserved data area is fixed across the CP1L, CP1H, CJ1M, and CP2E families:

• Word range: CIO 3100 to CIO 3199 (100 words total)
• Per-node width: 10 words
• Maximum nodes: 1 Master + 8 Slaves + 1 HMI (NT/NS series) = 10 logical participants
• HMI role: read-only with the Master only

PC Link therefore yields 9 × 10 = 90 active words on a fully populated bus plus 10 words of headroom within the same 100-word reserved block. No background interrupt, no message instruction (SEND/RECV), and no protocol macro is required to make data flow.

2. Hardware Requirements and Compatible CPU Units

The CP1W-CIF12 option board is the preferred choice for any multi-drop RS-485 PC Link because it provides 500 V rms isolation between the PLC bus and the field trunk, plus a switchable 220 Ω terminating resistor and a shield-ground terminal. The CP1W-CIF11 is acceptable for bench commissioning but should not be used in panels with long trunk runs or with significant common-mode noise.

3. RS-422A/485 Port Pin Assignment (CP1W-CIF11 / CP1W-CIF12)

The CP1W-CIF11 and CP1W-CIF12 expose a five-position screw terminal block. Pin assignments are identical on both boards; the only electrical difference is the isolation barrier on CIF12.

On the option board a slide switch selects the on-board terminating resistor (typically 220 Ω across RDA-/RDB+). Engage this terminator only on the two physical end nodes of the trunk. For a 2-wire RS-485 bus, internally RDA- is jumpered to SDA- and RDB+ is jumpered to SDB+ via the protocol mode setting; for 4-wire mode they remain separate.

4. Network Topology: 2-Wire (Half-Duplex) vs 4-Wire (Full-Duplex)

Two physical topologies are valid on RS-485 PC Link:

1. 4-wire / full-duplex (RS-422): four signal conductors, the Master's transmitter pair drives all Slaves' receiver pairs, and each Slave's transmitter pair drives the Master's receiver pair. Bus contention is impossible, so polling is deterministic.
2. 2-wire / half-duplex (RS-485): two signal conductors shared by every node's transmitter and receiver. Direction is controlled by the protocol; only one node drives the pair at a time.

Omron documents 4-wire wiring in the W462 Operation Manual. The 2-wire reduction is a field-proven arrangement that uses the same CP1W-CIF11/CIF12 terminal block. The simplified 2-wire scheme joins RDA- to SDA- and RDB+ to SDB+ at every node either by shorting the terminals externally or by relying on the bus-master direction discipline. In practice, technicians wire the trunk as A-to-A and B-to-B at every drop, which is functionally equivalent.

The maximum recommended trunk length is 50 m at 115 200 bps and up to 500 m at 19 200 bps or below. Use twisted pair (24 AWG typical) with shield grounded at one end only.

5. Bidirectional CIO Memory Map

Each node owns a dedicated 10-word slice of the reserved CIO 3100–CIO 3199 range. The Master always occupies the first slice; Slave 1 occupies the second slice; Slave 2 the third; and so on. Bidirectional data flow is achieved without any protocol change because every node simultaneously:

• reads the Master's slice (the words the Master placed on the bus during its last poll), and
• writes its own slice (the words the Master will read on the next poll).

The general formula for Slave n:

Slave n start word = 3100 + (n × 10)
Slave n end word   = 3109 + (n × 10)

Because every Slave also reads CIO 3100–CIO 3109, a Master-to-all-Slaves broadcast is automatic — there is no need to enumerate subscribers. The Master's only write action is to its own 10-word slice; all Slaves subscribe to those ten words.

6. CX-Programmer Configuration — Master

Open the project for the Master CPU and double-click Settings → PLC Setup in the project tree. Locate the section for the port that carries the option board (typically Serial Port 2 Settings when a CP1W-CIF12 is mounted on option slot 1).

1. Mode: set to Serial PLC Link Master.
2. Baud rate: select 115200, 57600, 38400, 19200, 9600, or 4800 bps. All nodes must match.
3. Highest PLC Link Node Number: enter the highest Slave node number (1–8). With eight Slaves, set 8. With one Slave, set 1. The Master only polls nodes 1..N, reducing cycle time.
4. Link Words per Node: enter 10 (default; 10 is the only supported value for PC Link).
5. Parity: set to Even (default).
6. Stop bits: 2.
7. Transfer the new PLC Setup to the CPU and cycle power (OFF → ON).

The Master takes the role of bus arbitrator. It writes CIO 3100–CIO 3109 to all Slaves on every poll and reads each Slave's slice in sequence.

7. CX-Programmer Configuration — Slave

1. Mode: set to Serial PLC Link Slave on the corresponding port.
2. Baud rate: must match the Master exactly.
3. Link Words per Node: 10.
4. Node number: assign 1–8 by setting Highest PLC Link Node Number = 1 on each Slave (the parameter is repurposed as the Slave's node address in Slave mode). All Slaves should show 1; the Master uses the polling list to address them by their position in the list, not by this parameter.
5. Transfer and cycle power.

In Slave Ladder code, read incoming Master values from CIO 3100–CIO 3109:

// Slave 1: copy Master's first word into a working area
LD   P_On
MOV(021) CIO3100   D100

And write outgoing data to the Slave's own slice CIO 3110–CIO 3119:

// Slave 1: push a status word and a process value to the Master
LD   P_On
MOV(021) W0.00     CIO3110.00  ; status bit
MOV(021) D200      CIO3111     ; process value

8. Wiring Procedure for Half-Duplex 2-Wire RS-485

The following procedure covers a two-node bench (Master CP1L + one Slave CP1L). For multi-drop, repeat the trunk tap at every Slave and enable the terminating resistor only on the two physical end nodes.

1. Power down both PLCs. Mount a CP1W-CIF12 (or CIF11) on the option-board connector of each PLC. Verify the board is fully seated; the CPU will not detect it otherwise.
2. Set the on-board terminating-resistor switch to ON on both end nodes. For a multi-drop bus, leave it OFF on every middle node.
3. Wire the trunk with 24 AWG twisted pair. Connect signal conductors first, shield last:

CP1L Master (CP1W-CIF12)         CP1L Slave (CP1W-CIF12)
+-------------------+             +-------------------+
| RDA- (1)  ----+   |             |   +---- RDA- (1) |
| RDB+ (2)  ----+---+----- A -----+---+---- RDB+ (2) |
| SDA- (3)  ----+   |             |   +---- SDA- (3) |
| SDB+ (4)  ----+---+----- B -----+---+---- SDB+ (4) |
| FG  (5)  ---------+----- SH ----+----------------+
+-------------------+             +-------------------+

An equivalent wiring that some technicians prefer is the A-to-A / B-to-B cross-connection scheme:

Master                  Slave
SDB+  -----------  SDA-  &  RDB+
RDB+  &  SDA- ----  RDA-  &  SDB+

This explicitly bridges the receive and transmit pairs at every drop, which is required when the option board does not internally strap RDA-/SDA- and RDB+/SDB+ together. The electrical result is identical to the straight-through trunk above; the cross scheme is more tolerant of mixed CIF11/CIF12 boards.

4. Connect FG/shield at one end only (Master end is the conventional choice). Do not ground both ends — this creates a ground loop that injects common-mode noise and breaks RS-485 signaling.
5. Power up the Slave first, then the Master. The Master's PC Link LED indicator (CP1L: COMM indicator on the option board, or the serial-port active flag A392.04) should begin blinking.
6. In CX-Programmer, connect to the Master and watch the PC Link Active Flag in the Auxiliary Area (see Section 9). When the flag transitions ON, data exchange is live.

9. LED Diagnostics and Status Flags

The first thing to check after a poll misses is the per-Slave participation bits. If A310.02 (Slave 3) is OFF while the rest are ON, the problem is localized to the Slave 3 node, the cable run to it, or its configuration. If all bits are OFF, the problem is at the Master or the trunk itself.

10. Cycle Time and Refresh Behavior

Each PC Link poll cycle consists of one Master transmission plus one response from each registered Slave. The wall-clock refresh period for the Master's CIO 3100–CIO 3109 buffer is therefore:

T_refresh = (1 + N_slaves) × t_frame
t_frame ≈ (1 / baud) × (10 words × 11 bits + overhead) ≈ 1.2 ms at 115200 bps, 10 words

With 8 Slaves at 115 200 bps, full-link refresh is roughly 10–15 ms. The data is not refreshed instantaneously when Ladder writes to CIO 3100..3109 — the CPU buffers the new values until the next poll slot. For deterministic timing in motion or interlocking code, gate on the A392.04 edge or the per-Slave participation bit to ensure the data you read is from a complete frame.

11. Troubleshooting Matrix

12. Cross-Platform Compatibility and Limits

PC Link is supported on the following CPU families per Omron documentation:

• CP1L — M/EM/EL types, via CP1W-CIF11/CIF12 on option slot
• CP1H — X/Y/XA types, via CP1W-CIF11/CIF12 or onboard RS-422A/485 (XA only)
• CJ1M — CPU11/12/13/21/22/23, via CJ1W-SCU21/41 Serial Communication Unit

Mixing families on the same PC Link bus is supported as long as baud, parity, and protocol mode match. The 10-word slice model is identical across families, so the CIO allocation described in Section 5 applies regardless of which CPU is Master or Slave.

For applications that exceed PC Link's 100-word reserved area or its 8-Slave ceiling, migrate to EtherNet/IP (CP1L-EM/EL, CP1H-Y, CJ1M-ETN) or Controller Link. PC Link is intentionally simple and is best suited to small, fixed-topology networks where the cost of a SCU/ETN21 would not be justified.

13. Safety and Commissioning Notes

• Power sequencing: bring up Slaves before the Master so the Master's first poll finds valid responders and the participation flags latch ON.
• Termination: 220 Ω across the pair at the two physical end nodes only. A middle node with termination loaded drops the bus impedance and causes reflections.
• Shield grounding: one end only. If the cabinet has a clean ground bar, terminate the shield there. If the field cable tray has its own ground, terminate at the entry point of the cabinet and not at the field device.
• Cable selection: use a twisted pair rated for the environment. Belden 9841 or 3106A are common field choices; any equivalent 100–120 Ω characteristic impedance cable will work.
• Surge protection: for trunk runs that leave the building, add an RS-485 surge arrester (Phoenix Contact PT-IQ-5-HF+F or equivalent) at the cabinet entry.
• Validation: before deploying, force known values into CIO 3110 on Slave 1 and confirm the Master reads the same value from CIO 3110 within one poll period. Repeat for every Slave.

For full protocol details and timing diagrams, refer to the Omron Industrial Automation documentation portal, specifically the CP1L CPU Unit Operation Manual (W462) and the CP1L CPU Unit Hardware Manual (W451). CX-Programmer operation is documented in the CX-Programmer Operation Manual (W446).

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