OMRON CS1G Long Delay Timer: Cascading Counters Beyond 1 Week

OMRON CS1G Long Delay Timer: Cascading Counters Beyond 1 Week

1. Overview: The 1-Week Barrier on CS1G

The OMRON CS1G series CPUs (CS1G-CPU42, CS1G-CPU43, CS1G-CPU44, CS1G-CPU45, plus the -V1 revisions and the CS1G-H variants) implement timer and counter instructions around a 4-digit BCD set value (SV) with a maximum of #9999. At the smallest practical resolution of 0.1 s, a single TIM instruction can hold 999.9 s, or roughly 16.6 minutes. When two instructions are chained (e.g., a 1-minute pulse driving a CNT), the user-visible ceiling is 9999 × 60 s = 599,940 s, which is 166.65 hours or about 6.94 days — still well short of a 3-month alarm requirement (≈ 7,776,000 s or 90 days).

This reference covers five field-proven techniques to obtain multi-month delays on CS1G hardware without resorting to PC-based supervisory timers or external hard-wired relays:

1. Cascading CNT counters driven by the built-in 1-second pulse flag
2. Binary accumulation (+L) with a 1-second pulse, comparing the resulting double-word against a 3-month constant
3. The dedicated TIML "Long Timer" instruction with an 8-digit BCD set value
4. The totalizing TTIM instruction, reset only by the alarm condition
5. Date/time comparison against the CS1G internal clock (words A351–A354) using the SEC instruction

A cross-platform comparison table is also provided so engineers migrating from or to Allen-Bradley CompactLogix, Siemens S7-1200, or AutomationDirect Do-more / CLICK PLCs can choose the path of least resistance on each platform.

2. Prerequisites

• CPU: CS1G-CPU42 / CPU43 / CPU44 / CPU45 (or -V1 / -H suffix). I/O capacity up to 960 points (CPU44) or 5120 points (CPU45).
• Programming software: CX-Programmer 9.6 or later. CX-One v4.6x is recommended for offline simulation with CX-Simulator.
• Memory: Minimum 4 free data-memory (D) words for accumulator, target, and clock buffer; minimum 2 free CIO words for the counter pair.
• Output: 1 free output bit, e.g., CIO 100.00, for the alarm coil.
• Tools: USB-to-Serial (CS1W-CIF31) or Ethernet (CS1W-ETN21) for upload/download.
• Documentation: OMRON CS1 Series Operation Manual (W447-E1) and Programming Manual (W340-E1) for ladder reference.

3. CS1G Timer and Counter Maximum Limits

Knowing the upper bound of each instruction is mandatory before selecting a method. The following table summarizes the limits as documented in the CS1 Series Programming Manual (W340-E1-08). All BCD-form instructions use # prefix; all binary-form instructions use & prefix and accept a 16- or 32-bit value.

The TIML instruction is the closest single-instruction match for a 3-month (~90-day) alarm and does not require additional ladder logic. It consumes two consecutive data words for the set value (low/high word) and two consecutive data words for the current value (low/high word). For a 3-month set value the SV is #0000 7776 000 (≈ 90 days × 86,400 ÷ 1000 = 7,776 × 1000 tenths-of-a-second), entered as #0007776000 in the low word / #0000 in the high word, or simply as #0000 7776 0000 in the user-typed 8-digit field.

The other instructions top out between 0.0076 days (TIMHX) and 6.94 days (a 1-minute pulse driving a CNT with SV 9999). For multi-month applications the ladder designer must therefore either escalate to TIML, accept a multi-stage cascade, or shift the timebase to a clock comparison.

4. Method 1 — Cascading Counters Using 1-Second Pulse and Binary Accumulation

The cleanest cascade on CS1G uses the standard P_1s conditional pulse flag at CIO 199.02 (older firmware) or CIO 102.02 (CS1G standard, also accessed as the special relay A200.02). The pulse is active for one scan period every 1.0 s. Driving a binary increment instruction from this pulse produces exactly 3,600 increments per hour, 86,400 per day, and 7,776,000 per 90 days.

4.1 Required memory map

4.2 Ladder logic — Section A (initialize on first scan, accumulate every second)

| P_First_Cycle       |---@MOVL(&0,    D0)               ; ELAPSED_S = 0
|                     |---@MOVL(&7776000, D2)           ; TARGET_S = 7,776,000 (= 90 days × 86,400)
| P_1s (A200.02)      |---@+L(&1,    D0, D0)            ; ELAPSED_S = ELAPSED_S + 1  (binary DINT)
|                     |     D0 = lower word, D1 = upper word
|                     |     P_1s -> 1 increment / s, max = 9,999,999,999 s (> 300 yrs)
|                     |--->L(  D2, D0)                  ; if ELAPSED_S >= TARGET_S
|                     |    --- ALARM_3MO                ; set alarm coil

4.3 How to enter this in CX-Programmer

1. Open the project, navigate to a new ladder section, and insert rung 1.
2. Click the leftmost contact, type P_First_Cycle (or insert a normally-open contact and assign it to A200.15).
3. Insert the @MOVL instruction, set Source &0, Destination D0. Set the differentiation option to "@" (rising edge).
4. Insert a parallel contact P_1s (or address A200.02).
5. Insert the @+L (double-word binary add, differentiated): Source A &1, Source B D0, Result D0. CS1G treats D0/D1 as a 32-bit signed integer (DINT).
6. Insert >L (32-bit binary compare): left D2, right D0. The output enables the alarm coil CIO 100.00.

4.4 Verification

For a 90-day alarm you cannot wait 90 days to confirm timing. Use one of the following shortened validation runs:

1. Constant substitution. Temporarily load TARGET_S = 60, run for 60 s, confirm the alarm coil energizes.
2. CX-Simulator accelerated run. Set the CS1G clock to 11/01/2024 12:00:00, force D2 = 7776000, then advance the simulator clock by 90 days using CX-Simulator's date offset.
3. Edge inspection in Monitor mode. Place the cursor on D0 in the ladder, switch to Hex/Decimal/Binary display, and verify the increment by exactly +1 each second.

5. Method 2 — Cascading BCD CNT Stages

If the application requires retentive counter behavior (survives power-cycle, no PC clock available) and the engineer prefers the visible, discrete CNT element to a DINT accumulator, cascade multiple CNT blocks.

5.1 Three-stage cascade (second → minute → hour → day)

; Stage 1 — counts 60 seconds
|  P_1s (A200.02)   |---[ CNT001 #0060 ]    ; 0–60 s
|  RESET_SYS        |---| |                ; Reset input (high → CNT=0)

; Stage 2 — counts 60 minutes
|  CNT001 carry (C1) |---[ CNT002 #0060 ]   ; 0–60 minutes
|  RESET_SYS         |---| |

; Stage 3 — counts 24 hours
|  CNT002 carry (C2) |---[ CNT003 #0024 ]   ; 0–24 hours
|  RESET_SYS         |---| |

; Stage 4 — counts 90 days
|  CNT003 carry (C3) |---[ CNT004 #0090 ]   ; 0–90 days
|  RESET_SYS         |---| |
|  CNT004 carry (C4) |--- ALARM_3MO         ; Alarm when CNT004 reaches 90

Each stage uses a 4-digit BCD SV. The PV and the carry bit (the same number as the counter, e.g., C1 for CNT001) form the next stage's input. Total resolution is 1 s; total range is 60 × 60 × 24 × 90 = 7,776,000 s — exactly 90 days.

5.2 Resolving the BCD overflow issue for >9999-day stages

BCD counters overflow at 9999. For >9,999 counts the engineer must either swap to CNTX (binary counter, max 65,535) or break the cascade again. The 90-day requirement stays well below 9,999 hours/days in any single stage, so a 4-stage BCD cascade is sufficient and remains in standard BCD ladder — the easiest visual layout for maintenance technicians trained on BCD CNT blocks.

6. Method 3 — TIML Long Timer (Single Instruction)

The TIML instruction is the textbook answer for delays between 1 hour and 115 days. It accepts an 8-digit BCD set value and an 8-digit current value, both stored as two consecutive data words.

6.1 Memory layout

6.2 Ladder

| START_3MO       |---[ TIML #0000 7776000 D10 ]   ; SV = 7,776,000 (×0.1 s) = 777,600 s
|                  |       ^SV low   ^SV high       ; Wait: 7,776,000 × 0.1 s = 777,600 s = 9 days only
|                  |
; -- CORRECTED for 90-day delay --
| START_3MO       |---[ TIML #0007 7760000 D10 ]   ; SV = 77,760,000 (×0.1 s) = 7,776,000 s = 90 days
|                  |       ^SV low   ^SV high       ; Low word = 7760000 BCD, High word = 0007 BCD
|                  |
|                  |--- TIML_DONE (output bit allocated by CX-Programmer)
| TIML_DONE       |--- ALARM_3MO                   ; latched alarm output

6.3 CX-Programmer entry

1. Insert TIML. The operand selector dialog shows S (set value first word), N (first word of two-word SV area), and one input bit.
2. For a 90-day timer: SV = 90 × 86,400 × 10 (tenths of a second) = 77,760,000. In BCD that is #0007 7760000, entered with the low word = #7760000 and the high word = #0007.
3. Allocate PV to two free data words (e.g., D12 low / D13 high).
4. The completion bit is automatically allocated by CX-Programmer in the work area; for clarity you can map it to a user-defined bit like W0.00.

6.4 Why this is the cleanest single-instruction solution

• Retentive across scan — no pulse-edge handling required.
• PV can be monitored in CX-Programmer to show elapsed time in seconds, minutes, or days using a custom display.
• Resolution 0.1 s. Range 0–9,999,999.9 s (115.74 days) covers a 90-day alarm with 25 days of margin.
• If the requirement ever exceeds 115.74 days, switch to Method 1 (binary accumulator) which has no practical upper bound.

7. Method 4 — Clock-Based Date/Time Comparison

The CS1G has an internal battery-backed clock accessed through auxiliary area words A351–A354. The SEC instruction converts the binary second-of-day to "seconds since 1970-01-01 00:00:00 UTC" (or local time, depending on A351.07 configuration). This is the only method on CS1G that survives PLC mode changes, power cycles, and battery replacement without loss of timing — provided the clock is kept correct.

7.1 CS1G clock auxiliary word map

7.2 Ladder logic — capture start, compute target, compare once per minute

; Rung 1 — On first cycle, store initial SEC value
| P_First_Cycle |---@MOV(&0,  D4)               ; RESET_LATCH flag
| P_First_Cycle |---@SEC(  D100, A353, A351)     ; Read A351–A353 into D100:D101 as DINT seconds
|               |                              ; Note: see W340 manual for exact SEC operands

; Rung 2 — Once per minute, refresh "now" and compare against start + 7,776,000
| P_1min (A200.04) |---@SEC(D100, A353, A351)    ; NOW_S = seconds since epoch
| P_First_Cycle    |---@MOVL(D100, D102)         ; START_S = NOW_S
| P_First_Cycle    |---@+L(&7776000, D102, D104) ; TARGET_S = START_S + 90 days

| always_on         |--->L(D100, D104)           ; if NOW_S >= TARGET_S
|                   |    --- ALARM_3MO           ; raise alarm (sticky until reset)

7.3 Why use P_1min instead of every scan

The SEC instruction produces integer seconds, so the comparison value D100 only changes once per minute. Executing the comparison every scan wastes cycles; gating with P_1min (special relay A200.04) limits the comparison to once per minute. For sub-minute precision, use P_1s instead.

7.4 Edge case — battery removal and clock drift

CS1G battery model CS1W-BAT01 holds the clock for ~5 years at 25 °C. If the battery dies, the clock reverts to 00:00:00 1970-01-01 and the A351.06 "battery low" flag sets. An application that depends on absolute date must:

1. Monitor A402.04 (battery error) and raise an alarm.
2. Block the 3-month alarm from triggering prematurely — gate ALARM_3MO with "clock valid" derived from A351.07 = 0 and A402.04 = 0.
3. Use the DATE instruction (CS1 firmware ≥ v2.0) to set the clock from an HMI on startup.

8. Method 5 — Totalizing Timer TTIM with Retentive Cascade

The TTIM instruction has two inputs: an "increment" input and a "reset" input. The PV accumulates as long as the increment input is ON; the PV stops when the increment input is OFF; the PV resets to zero when the reset input is ON. Because the PV persists while the input is OFF, the instruction is naturally suited to cumulative time across intermittent process events.

8.1 Typical use — "process run hours" accumulator

Many 3-month service-due alarms are actually "3 months of process run time" rather than calendar 90 days. In that case the timer should accumulate only when the equipment is actually operating.

; Accumulate process run time up to 7,776,000 s = 90 days
| EQUIP_RUN (CIO 0.02) |---[ TTIM #00007776 D20 ]   ; 7,776 × 0.1 s = 777.6 s per TTIM stage
|                      |                              ; Use 7,776, not 77,760,000 — TTIM is 4-digit BCD only
| ALARM_3MO_RST        |---| |

; Stage 2 — count TTIM completion events (each = 777.6 s) until 10,000 events
| TTIM done (T1)       |---[ CNT010 #10000 ]
| ALARM_3MO_RST        |---| |
| CNT010 done (C10)    |--- ALARM_3MO

Total: 7,776 × 10,000 × 0.1 s = 7,776,000 s = 90 days of process run time, with the alarm latched until ALARM_3MO_RST clears the counter. The same pattern can be extended indefinitely by cascading another CNT stage at the second level.

9. Cross-Platform Reference: Long-Delay Timers on Other PLCs

Engineers migrating logic between platforms should be aware of the following equivalents so the same 90-day requirement can be met with the minimum amount of ladder logic on each system.

The Allen-Bradley, Siemens, and Mitsubishi platforms can implement a 90-day alarm in a single tag-based timer instruction because their set-value data type is a signed 32-bit integer with millisecond resolution. CS1G's older BCD-oriented set values require either TIML or a cascade, which is why this article focuses on CS1G-specific ladder patterns.

10. Verification and Commissioning

A multi-month alarm cannot be validated by waiting. Use the following accelerated verification procedure before handing the system over to operations.

10.1 Commissioning checklist

10.2 Inline ladder timing diagram (Method 1)

10.3 What to capture in CX-Programmer documentation

1. Save the rung text or rung comment explaining the 90-day target.
2. Add a data-trace to D0 and CIO 100.00 so the trace file shows the alarm event with timestamp.
3. Print the ladder with symbols and rung comments; attach to the project functional specification.
4. Export the I/O comment file as .CIF and archive with the project backup.

11. Edge Cases and Field Notes

11.1 Scan time vs. 1-second pulse

If the CPU scan time exceeds 1.0 s, the P_1s flag is missed entirely. CS1G CPU44 default scan time is ~0.3 ms for a 10K-step program; even at 100K steps with extensive floating-point math, scan stays below 30 ms. For very large programs (CS1G-CPU45 with 240K steps and heavy motion blocks) verify with the SYSTEM → Cycle Time display in CX-Programmer Monitor mode that cycle time stays below 700 ms; otherwise use a slower pulse like P_2s and adjust the constant accordingly.

11.2 Daylight saving and time zones

The CS1G internal clock does not auto-adjust for daylight saving time. If the facility observes DST, the SEC-based method (Method 4) will shift the elapsed target by 1 hour twice per year. For absolute calendar accuracy, either disable DST on the system clock and have the HMI display local time as a fixed offset, or compute the 90-day target in the HMI and pass it as a DINT into the PLC.

11.3 Resetting the cascade without losing accumulation

Often the operations team needs to reset a 3-month timer for one specific cycle (e.g., after a maintenance campaign). Provide a dedicated, named reset bit such as W10.00 ALARM_3MO_RST that:

• Clears D0:D1 (ELAPSED_S) to zero.
• Resets CNT001–CNT004 in cascade configurations.
• Requires a momentary push, not a maintained contact, to prevent an immediate re-trigger.

11.4 What happens on mode change to PROGRAM

In PROGRAM mode the P_1s pulse continues to run because the special relays are driven by the CPU's hardware clock, not by program execution. However, the @+L instruction only executes when the CPU is in RUN or MONITOR mode. So a CPU that sits in PROGRAM for 30 minutes will lose 30 minutes of accumulation in Method 1. Document this carefully if the application is sensitive to cumulative run hours; consider switching to Method 4 (clock comparison) which is immune to mode changes.

11.5 HMI scaling for elapsed-time display

A 32-bit binary second counter (0 to 7,776,000 s) exceeds the 16-bit integer range. To display "days remaining" on an HMI:

1. Use the /L (double-word binary divide) instruction to compute D6:D7 = D0:D1 / 86400 (days).
2. Use the MOD instruction or a second /L to compute the remainder (hours).
3. Send D6 and the remainder to the HMI as separate tags.

On a 16-bit HMI panel (e.g., NS-series) the value 7,776,000 exceeds the 65,535 ceiling, so scaling is mandatory.

12. Frequently Asked Questions