PCS 7 V9.0 SP2 APL Block Deployment: Cyclic OBs and ET200SP HA

Overview

SIMATIC PCS 7 V9.0 SP2 with the Advanced Process Library (APL) imposes strict constraints on where and how function blocks can be instantiated and downloaded. The APL documentation set A5E39147331-AC requires that blocks such as Pcs7AnIn (FB 1869), Pcs7DiIn, Pcs7AnOu, and Pcs7DiOu be installed inside a cyclic interrupt OB (OB30 through OB38), not in OB1. CPU 410-5H (and the wider AS 410 family) further restricts the download path: only the CFC editor, SFC, NetPro, or HW Config can perform a download. A download from the S7 program folder (FBD/LAD source) is rejected by the firmware, even if the project file is renamed to look like an S7 project. This reference consolidates the deployment rules, licensing model, ET200SP HA compatibility, and verification procedures for engineers commissioning a PCS 7 V9.0 SP2 project.

Prerequisites

• SIMATIC PCS 7 V9.0 SP2 engineering station with the AS/OS Engineering license installed. Order number 6ES7658-5AX58-0YA5 (also written 6ES76585AX580YA5) grants both AS and OS engineering rights, including CFC and SCL compilation rights, on a single floating license.
• PCS 7 APL library installed and registered in the master data library of the project.
• AS 410 controller (CPU 410-5H, CPU 410E, or CPU 410 SMART) for the strict-CFC rule. CPU 417-4H accepts partial downloads from LAD/FBD sources and may be used when gradual migration is required.
• STEP 7 V5.6 or PCS 7 engineering toolset that matches the controller firmware baseline.
• For ET200SP HA installations: a configured PROFINET IO subnet with the HA station assembled in HW Config and the matching IM 155-6 PN HA interface module.

APL Block Installation in Cyclic Interrupt OBs

APL documentation A5E39147331-AC section "Use the CFC editor to install the block in a cyclic interrupt OB (OB30 to OB38)" is a hard runtime requirement, not an editorial guideline. The block's internal timing structures (cycle-time normalization, ramp limiting, mode-tracking time bases, alarm deadbands) are computed against the OB run-time interval. When the same block executes inside OB1, the timer math degrades in two ways:

1. Time-base drift. OB1 runs at the priority-1 cycle, which is influenced by image-partition updates and bus communication. APL blocks call TIME_TCK or system clock SFCs that assume a deterministic interval; OB1 jitter propagates into the LAG filter of Pcs7AnIn and the PID step response of Pcs7Cntrl.
2. Watchdog trip. OB1 priority (1) is shared with many lower-priority services; if OB1 scan time exceeds the configured max cycle, the CPU enters STOP with diagnostic event SF: cycle time exceeded.

CFC vs FBD/LAD Programming Paths in PCS 7

FBD/LAD source code is allowed inside PCS 7, but only as a sub-chart that is referenced from a CFC chart. The CFC editor wraps the FBD/LAD network into a CFC-compatible block instance with I/O interconnects and run sequence. Trying to download a chart that lives outside the CFC container fails differently on each controller family:

The CPU 410 family adds an integrity check that compares the chart's signature against the CFC compiler output. The signature is regenerated whenever the CFC run sequence is edited. Bypassing the check by switching the project type from PCS 7 to S7 is permitted on CPU 417 but not on CPU 410. On CPU 410 the firmware examines the S7 program container and refuses any block whose run-time attribute is missing the CFC container stamp.

CPU410-5H Download Restrictions

CPU 410-5H was designed from the start as a PCS 7 controller with safety integration (H-system). Siemens removed the partial download path from the standard STEP 7 download dialog for this family. Permitted download sources:

• HW Config — for hardware changes only.
• NetPro — for connection table updates.
• CFC / SFC editor — for chart and sequential function chart changes.
• PCS 7 OS / WinCC Explorer — for OS-side picture tree updates.

The diagnostic buffer entries associated with rejected downloads are 0x05F2 0x0001 "Download canceled — invalid container" and 0x05F2 0x0002 "Download canceled — CFC signature missing". If you encounter these entries, do not attempt to switch the project type; rebuild the chart inside CFC and re-download.

APL Block Compatibility with ET200SP HA

The manual entry for Pcs7AnIn (FB 1869) reads: "Signal processing of an analog input value of S7-300/400 SM analog input modules including ET 200M Ex-io module in °C." Field experience and the latest readme file confirm that the same FB 1869 also supports ET200SP HA, ET200SP, ET200MP, and ET200pro analog input channels. The text in A5E39147331-AC is historical and has not been refreshed to list every distributed I/O family added since APL V8.0.

The following block-to-channel matrix applies for ET200SP HA projects in PCS 7 V9.0 SP2:

PCS 7 V9.0 SP2 Licensing Model

The licensing model groups PCS 7 engineering rights into two floating license buckets. AS/OS Engineering (6ES7658-5AX58-0YA5) covers:

• CFC / SFC editor (compile, download, run sequence)
• SCL editor
• WinCC / PCS 7 OS picture editor
• HW Config, NetPro, plant view

The standalone CFC license (6ES7658-1EX58-0YA5) covers CFC/SFC only and is typically added when an external integrator needs chart work but not full AS/OS engineering rights. For a single engineering station the AS/OS Engineering bundle is the more economical choice and supersedes the standalone CFC order.

Configuration Procedure

1. License check. Open the Automation License Manager and confirm the AS/OS Engineering license 6ES7658-5AX58-0YA5 is present and not in the grace period. Grace period expiry locks the CFC download dialog.
2. Project type check. In SIMATIC Manager, right-click the project > Object Properties > confirm PCS 7 V9.0. Do not toggle to S7 type if the target is CPU 410.
3. Master data library. Verify the APL master data library is installed and the block version matches the engineering toolset. Open CFC > Library > APL > confirm FB 1869 revision is compatible with V9.0 SP2.
4. Insert chart into a cyclic OB. In the plant view, open the S7 program > Charts > right-click > Insert New Chart > assign OB35 (default) or another OB30-OB38 per cycle requirements. Drop Pcs7AnIn onto the chart sheet.
5. Wrap any FBD/LAD networks. If you wrote block logic in FBD/LAD, drop the compiled FB onto a CFC sheet and interconnect the inputs and outputs from there. The block folder copy alone is not enough.
6. Configure ET200SP HA channel. In HW Config assign the AI module's input range, scaling, and channel error behavior. In the CFC chart sheet, wire the process value, channel error, and substitute value inputs.
7. Compile and download from CFC. Click the CFC download icon or use menu > PLC > Download. Do not invoke the S7 program-level download dialog.

Verification Checklist

Troubleshooting Matrix

Practical Field Notes

• Migrating from CPU 417 to CPU 410. Existing charts that were downloaded from the S7 block folder on a 417 will need to be re-compiled via CFC before the same project can run on a 410. Plan at least one full stop/start cycle for the re-compile.
• Mixed phase OBs. You can split fast loops (OB30, 10 ms) from default loops (OB35, 100 ms) and run them on the same CPU 410. The run sequence in CFC controls the phase relationship; verify it via the CFC runtime monitor.
• Update discipline. When upgrading to PCS 7 V9.1 SP2, install the CFC V9.0 SP8 Upd9 patch listed in the V9.1 SP2 Software Updates entry. APL block revision counters shift with this patch and old charts may report "incompatible revision" until re-compiled.
• Faceplate style switch. If you switch faceplates from Classic style to APL style, do so chart-by-chart and verify the OS server sees the new picture block. The PCS 7 Readme V9.0 notes that only one faceplate style variant can be installed at a time on a given OS server.

FAQ