PTO Pulse Generation Limits with 6ES7 322-1BH10-0AA0 SM 322 DO

Problem: PTO Pulse Generation on 6ES7 322-1BH10-0AA0

The combination of a CPU 315-2DP (6ES7315-2AG10 or similar), an IM 153-1 ET 200M head, and the digital output module SM 322; DO 16 x DC 24 V / 0.5 A High Speed (6ES7322-1BH10-0AA0) is frequently wired to drive stepper motor amplifiers through the step/direction interface. Engineers regularly attempt to produce pulse trains of 500 Hz, 800 Hz, or higher from the standard DO backplane of the S7-300, only to find that the produced step rate collapses or the pulse-train duty cycle distorts once the OB1 scan time reaches ~17 ms.

The defect is not in wiring, ground loops, or field-device termination - it is a fundamental ceiling imposed by three coupled timing limits:

1. OB scan period on the CPU 315-2DP (no OB38 / OB1x < 10 ms available).
2. Output reaction time of the SM 322-1BH10 output stage (0→1 and 1→0 propagation).
3. Stepper driver input conditioning (optocoupler + debounce / Schmitt trigger RC), which further divides the achievable pulse rate.

SM 322-1BH10-0AA0 Module Specifications

The High Speed variant 6ES7322-1BH10-0AA0 differs from the standard 6ES7322-1BH01-0AA0 in switching performance and group isolation. Key parameters that drive PTO feasibility:

Source: Siemens product master data – 6ES7322-1BH10-0AA0.

CPU 315-2DP Cycle Time and OB Limitations

The CPU 315-2DP belongs to the S7-300 family with integrated PROFIBUS-DP master. Its cyclic interrupt OBs have these fixed clocking boundaries:

For the SM 322-1BH10-0AA0 driving a stepper pulse stream, the relevant OB is OB35. The minimum OB35 period the CPU 315-2DP will accept is 1 ms, but only if the configured OB35 execution time plus the main scan stays below the period. With a typical OB35 of 5–10 ms and an OB1 of 17 ms, the effective half-period ceiling for a toggled output is roughly 17 ms × 0.5 ≈ 8.5 ms (low → high → low), i.e. ≈ 60 Hz in raw user-program toggling.

Why the SM 322-1BH10 Cannot Reach 800 Hz Reliably

Three independent stop bands each reject the 800 Hz target:

2.1 OB clocking stop band

To toggle an output at 800 Hz with 50 % duty, the application must change the output bit every T/2 = 625 µs. No OB on the CPU 315-2DP can fire that fast without leaving CPU time for OB1, PROFIBUS DP cycle, and the S7 timer / counter updates.

2.2 DO reaction-time stop band

The 6ES7322-1BH10-0AA0 has typical propagation of 100–300 µs per edge. For an 800 Hz square wave (1.25 ms period, 625 µs half-period), the cumulative lag on the rising edge plus the falling edge is up to 600 µs. The duty cycle will skew from 50 % to roughly 20 %/80 % depending on direction, which most stepper drivers interpret as a step on the rising edge only and still accept, but the step rate is reduced to what the module can sustain, typically 500 Hz – 1 kHz.

2.3 Driver input stop band

Stepper-driver optocoupler inputs normally include an RC filter of 10 µs – 100 µs to reject noise. Combined with the optocoupler rise/fall time, the effective input bandwidth is 50 kHz – 200 kHz, which is not the problem. The real stop band is the way the user toggles the bit. Toggling inside OB1 at 17 ms scan → 29 Hz is the most common failure mode and matches what the source reports.

Calculating Maximum Achievable Frequency

Use this framework to size any proposal before commissioning:

F_max = 1 / ( 2 × (T_ob + T_do + T_driver) )

Where:

• T_ob = OB scan period in seconds (OB35 for periodic).
• T_do = sum of 0→1 and 1→0 propagation of the DO module.
• T_driver = optocoupler + RC time constant of the driver input.

Example A: 800 Hz target, OB35 = 10 ms, SM 322-1BH10-0AA0, typical driver

• T_ob = 10 × 10⁻³ s = 10 000 µs
• T_do = 200 µs + 200 µs = 400 µs
• T_driver = 50 µs

F_max = 1 / (2 × (10 000 + 400 + 50) × 10⁻⁶) = 1 / 0.0209 ≈ 47.8 Hz

The OB clocking alone caps the result at ~50 Hz regardless of how "fast" the module is.

Example B: 800 Hz target, OB35 = 1 ms (lowest legal)

• F_max = 1 / (2 × (1 000 + 400 + 50) × 10⁻⁶) ≈ 345 Hz

Still short of 800 Hz. To hit 800 Hz with the SM 322-1BH10-0AA0, OB35 would need to drop to ~200 µs, which is below the CPU 315-2DP capability.

Hardware Alternatives for PTO Generation

When 250 Hz – 100 kHz step rates are required, replace the SM 322-1BH10-0AA0 with one of the following, in increasing order of performance:

Each FM 350/351/352/353/354 family module occupies one S7-300 slot and is parameterised through the dedicated FM setup interface in STEP 7 (HW Config → FM Properties). The FM 353 is the canonical drop-in for replacing a manual OB35 pulse loop with hardware-accelerated step generation that the CPU off-loads completely.

ET 200S 1STEP / 2STEP Drop-In on an Existing IM 153-1 Station

If the project is locked to PROFIBUS DP and the IM 153-1 must stay, the most cost-effective swap is to remove the SM 322-1BH10-0AA0 from its slot and insert an ET 200S pulse generator in an ET 200S sub-rack fed from the IM 153-1 DP/PA link. The 6ES7138-4DC00-0AB0 (1STEP) provides:

• One pulse/direction output, 24 V or RS-422 (5 V TTL).
• Resolution 32 bits, max output frequency 25 kHz (24 V) or 1 MHz (TTL).
• Integrated ramp generator (linear, jerk-limited).
• Hardware inputs for reference, encoder, and digital I/O.

It is configured via the GSD file SIEM8170.GSD and integrated as a PROFIBUS DP slave to the CPU 315-2DP. The user program exchanges 12 bytes of output / 12 bytes of input data via SFC 14 / SFC 15.

Software Compensation Patterns (When Hardware Swap Is Not Possible)

On a CPU 315-2DP that cannot be replaced, the highest pulse rate that can be obtained from an SM 322-1BH10-0AA0 without an FM module is in the 250 Hz – 500 Hz range, and only under strict conditions:

1. Configure OB35 to 1 ms in HW Config (CPU 315-2DP supports this).
2. Place all pulse logic in OB35. Do not call SFC 14/15, Profibus I/O consistency, or PID blocks from OB35.
3. Use a word-mask output and direct PQW to trigger the SET / RESET. The bit must be toggled inside the OB35 and not gated by an OB1 flag.
4. Use QPA (set) and QNA (reset) bit instructions on an immediate-write flag, e.g. SET / CLR on PIB/PQB with :P qualifier to bypass the process image and force the backplane update.
5. Hold OB1 to >100 ms and exclude the toggle from any conditional check that depends on OB1 scan.

Sample OB35 toggle snippet (ST):

// OB35 - pulse toggle at OB35 tick
IF OB35_FIRST_SCAN THEN
    i_state := 0;
END_IF;
i_state := 1 - i_state;
IF i_state = 1 THEN
    QP 0.0;       // immediate set, no PII update
ELSE
    RN 0.0;       // immediate reset
END_IF;

Stepper Driver Input Requirements

Before sizing the pulse source, validate the driver interface. Most stepper drives (Siemens FM STEP, Oriental Motor CVD, Linistepper, Nanotec, Leadshine DM, Schneider Lexium MDrive, etc.) present an optocoupler STEP input with the following electrical envelope:

A standard pattern is to drive the optocoupler LED from a 24 V output through a 1.8 kΩ – 2.2 kΩ current-limiting resistor. The optocoupler presents a near-resistive load to the SM 322-1BH10-0AA0 and therefore does not cause the inductive-load derating. The bandwidth ceiling is the CPU+OB cycle, not the module.

Verification and Commissioning Checks

Use this matrix after every change to confirm the PTO chain meets specification:

Recommended test sequence:

1. Power up the CPU and SM 322 with a 24 V dummy resistive load (e.g. 470 Ω, 1 W) instead of the stepper driver.
2. Program OB35 to 1 ms and toggle the bit at 250 Hz; observe on scope.
3. If the duty cycle is asymmetric or jitter > 20 %, the OB clock is the bottleneck. Migrate to FM 353 or ET 200S 1STEP.
4. Replace the resistive load with the stepper driver STEP input.
5. Confirm the driver reference-input pulses (DIR or CW/CCW) follow the expected 0/1 state.
6. Run a 30-minute continuous test. Monitor module diagnostics for SF = diagnostic interrupt, indicating short circuit or overload on the SM 322-1BH10.

Frequently Asked Questions