Reading ABB Drive Speed via S7-300 CPU 313C with FC105 Scaling

Problem Definition

An S7-300 CPU 313C is wired to an ABB drive (e.g., ACS355 or ACS800) and configured to read the motor speed through the analog input of the PLC. The STEP 7 standard library block FC105 "SCALE" is used to convert the raw integer value (PIW) read from the analog input into a real engineering unit in Hz. The reported symptom is that the FC105 output does not match the actual motor speed displayed on the ABB drive keypad: for example, the drive shows 25 Hz and FC105 returns a value of 25.3, while the raw word PEW 256 shows 116800 instead of the expected 27648 (which the engineer tried first as EW 256).

The defect is rarely caused by FC105 itself. It is caused by a combination of incorrect address mapping, wrong polarity selection, wrong analog range configuration on either the CPU 313C or the ABB drive, and a missing step in the conversion pipeline (PIW → INT → FC105 → REAL). This article walks through the diagnosis, the correct addressing, the parameter block for FC105, and the ABB drive analog output configuration needed to recover correct speed feedback.

Root Cause Analysis

Four overlapping root causes explain almost every FC105 speed-readout problem on a CPU 313C:

1. Wrong address type or wrong channel. EW 256 / PEW 256 is not the integrated analog input on the CPU 313C. The integrated analog inputs live in the process input image at PIW 752 through PIW 760. Reading an uninitialized process image word produces garbage (116800 = 0x1C800), which is the symptom reported.
2. Polarity mismatch. A 0 to 20 mA signal is unipolar (always positive), yet the BIPOLAR input of FC105 is left at TRUE. With TRUE, FC105 treats the value as -27648 to +27648, so a 10 mA signal at 13824 decimal is interpreted as the negative half of the bipolar range, scaling to a negative Hz value.
3. Wrong HI_LIM / LO_LIM. Using 100.0 / 0.0 will yield percent. Using 50.0 / 0.0 yields Hz only if the drive is configured to output 20 mA at parameter 20.02 MAXIMUM SPEED. If the drive's analog output max is left at 50 Hz but the motor nameplate max is 1450 rpm at 50 Hz, FC105 will still be correct, but the output will have a residual error of roughly ±0.3 Hz because the ABB internal scaling is rounded to 1 rpm.
4. Drive output configuration mismatch. The ABB ACS355 by default maps analog output 1 (AO1) to motor speed frequency, but it does not automatically link AO1 scaling to parameter 20.02 MAXIMUM SPEED; the user must set parameters 13.04 (AO1 minimum), 13.05 (AO1 maximum), and 13.07 (AO1 signal range = 0-20 mA).

CPU 313C Analog Input Architecture

The SIMATIC S7-300 CPU 31xC Technological Functions manual documents the integrated analog I/O of the CPU 313C (order number 6ES7313-5BF03-0AB0 and earlier variants) as follows:

For a 0 to 20 mA signal the wire pair connects to the I+ and I- terminals of the chosen channel. The analog common Mana (pin 20 of the front connector) must be referenced to the drive's analog common. Unused channels must be shorted at their common to suppress noise pickup, as recommended in the same manual.

The Siemens analog normalization is the same as for any SM 334 / SM 331 AI:

FC105 SCALE Block Parameter Mapping

FC105 is documented in the STEP 7 Standard Library reference (function blocks FC105 / FC106). The block call in OB1 or a cyclic OB looks as follows:

CALL FC 105
  IN     := MW100          // INT input from PIW (load via MOVE PIW-->MW)
  HI_LIM := 5.0E+01        // REAL, 50.0 for 50 Hz max speed
  LO_LIM := 0.0E+00        // REAL, 0.0
  BIPOLAR:= FALSE          // BOOL, FALSE for 0-20 mA unipolar
  RET_VAL:= MW102          // WORD return code (0 = OK, >0 = overflow)
  OUT    := MD104          // REAL output, e.g. 25.3 (Hz)

Internally FC105 computes:

OUT = LO_LIM + (IN - K1) / (K2 - K1) * (HI_LIM - LO_LIM)

where K1 = 0 and K2 = 27648 when BIPOLAR = FALSE, and K1 = -27648, K2 = 27648 when BIPOLAR = TRUE. For bipolar FC105 the input integer must be supplied as INT (signed). FC106 is the inverse function (REAL → scaled integer for output).

ABB ACS355 / ACS800 Analog Output Configuration

The LVD-EOTN97U-EN_REVA ACS800 speed-scaling note describes how the ABB drive maps its internal MAIN DS ACT1 / ACT2 frequency word to the analog output. For the ACS355 the equivalent parameter set is parameter group 13. The settings that fix the FC105 mismatch are:

Setting AO1 SIGNAL to one range on the drive while the CPU 313C is configured for another range will produce a consistent offset error. If the drive is set to 4-20 mA and the CPU is set to 0-20 mA, 4 mA will produce 1 / 5 scale (because 4 mA is at 0 in CPU range but at 0 % in drive range), so 0 Hz becomes 25 % of the PLC range, giving an 12.5 Hz offset at low speed. Always match both ends.

Wiring, Shielding, and Signal Integrity

The integrated analog inputs of the CPU 313C are referenced to Mana (analog ground). To keep noise-induced offsets out of FC105 (a typical 0.1 mA noise coupled into the analog loop produces about 0.25 Hz of displayed error at 50 Hz max), apply this wiring discipline:

1. Use a shielded, twisted pair cable from the drive's AO1 terminals to the CPU 313C AI terminals. Ground the shield at one end only — at the panel ground bar near the PLC — to avoid ground loops.
2. Connect the drive's analog common (often labeled AGND or AGND1) to Mana on the CPU 313C. If the drive and PLC are powered from different supplies, this link prevents floating common from clipping the analog signal.
3. Short any unused analog channel input to its own common on the CPU 313C side. The S7-300 manual specifically calls this out as a noise-reduction measure.
4. Place the analog cable in a tray separated from motor power cables and from any VFD output cabling by at least 200 mm. Crossings should be at 90°.
5. Verify the drive's analog output drive capability. The ACS355 AO1 source impedance is roughly 700 Ω max at 20 mA. The CPU 313C AI input impedance in current mode is 50 Ω typical, so voltage compliance on the drive is roughly 10 V at 20 mA — adequate for the loop.

A floating AGND or a missing Mana reference is the single most common cause of FC105 returning values that drift a few Hz between no-load and full-load, which is what produces the 25.3 display when the drive is actually outputting 25.0.

Step-by-Step Corrective Procedure

1. Stop the drive and PLC. Open the panel and confirm there is no active motion.
2. Open SIMATIC Manager → HW Config. Select the CPU 313C and open Properties → Analog Inputs. Set the channel wired to the drive (typically Channel 0 or 1) to Current, 0-20 mA (or 4-20 mA if you chose that). Save and download.
3. Wire the drive's AO1. Connect AO1+ to I+ of the selected CPU channel, AGND to Mana. Tie the shield to panel ground.
4. Configure the ABB drive. From the keypad navigate to parameter groups 13 and 20. Set 1304 = 0.0, 1305 = 100.0, 1306 = 103 (output frequency), 1307 = 0 (0-20 mA), 2002 = motor nameplate rpm, 2008 = 50.0 Hz.
5. Open the STEP 7 program. In OB1 add a MOVE instruction that copies the integer from the chosen analog channel to a flag word: L PIW 754 T MW 100. This forces the conversion into STEP 7's signed-INT representation, which is what FC105 expects.
6. Call FC105 with the parameters listed above (HI_LIM = 50.0, LO_LIM = 0.0, BIPOLAR = FALSE). Drive OUT into a real tag such as MD104.
7. Download and monitor. Use a VAT table on PIW 754 to confirm the raw integer; use a separate VAT table on MD104 to watch the FC105 output. With the drive at 0 Hz you must see PIW 754 ≈ 0 and MD104 ≈ 0.0.
8. Run a three-point verification — 0 Hz, 25 Hz, 50 Hz — and record both the drive display and the FC105 output.

Verification Procedure and Acceptance Criteria

After the corrective procedure, the following must hold across the operating range:

Any deviation larger than ±0.05 Hz at three points indicates one of: a noisy analog loop, an offset in the drive's DAC, or wrong polarity on FC105. The 0.3 Hz offset seen in the original report (25.3 vs 25.0) corresponds to a raw error of roughly 16 counts (≈ 0.116 mA), which fits both the ACS355 DAC quantization (12 bits across 0-20 mA = 4.88 µA/LSB) and the CPU 313C ADC quantization. To compensate, apply a one-point trim in the drive (parameter 1304 / 1305) or in the PLC (offset on MD104) rather than chasing hardware noise.

For HMI display, ROUND(REAL_TO_DINT(MD104)) before sending to the operator panel — engineers reading 25.3 on screen will call it a fault; displaying 25 masks the LSB-level noise without hiding real errors.

Resolution and Precision Optimization

If FC105 still shows a residual 0.3 Hz error after the steps above, apply these field-proven fixes:

• Use FC105 only at the analog front-end. Do not push the FC105 REAL output to a tag and then multiply elsewhere; chain the formatting (ROUND, TRUNC, REAL_TO_DINT) before the HMI tag so the HMI never sees a non-integer Hz value.
• Average the raw input. Insert a 4-to-8 sample moving average in the PIW-to-MW pre-stage if the value jitters visibly on the VAT table. This typically halves the displayed jitter without changing FC105 behavior.
• Switch to Profibus/Profinet if the 0.3 Hz error matters. Using the ABB drive's Profibus-DP process data word eliminates the analog chain entirely: word 1 of the PPO contains actual speed as a 16-bit signed value scaled by parameter 50.01 (Speed scaling). For the ACS800, MAIN DS ACT1 carries the same value; for the ACS350/355 the corresponding word is PZD2 / PPO word 1.
• Verify RET_VAL. If FC105's RET_VAL is non-zero, ignore the output entirely. RET_VAL codes are documented in the STEP 7 Standard Library reference and indicate ranges of OUT / IN overflow.
• Document the scaling choice. Place the equivalent of the formula above — for 0-20 mA, 0-50 Hz, bipolar = FALSE — into the project's HMI tag descriptor so that future maintenance understands why PIW 754 is no longer the raw display word.

Once these corrections are made, the original symptom (FC105 returning 25.300 when the drive shows 25.0) drops to ≤ 25.05 across the operating range, which is within ADC noise and acceptable for any drive-control HMI.

Frequently Asked Questions