Replacing S5 FC84 Division in S7-300/400 with /I Instruction

Overview

The S5 function block FC 84 performs a 16-bit signed integer division with explicit overflow and quotient/remainder zero flags. When porting an S5 program to an S7-300 or S7-400 controller using classic STEP 7 (SIMATIC Manager) or TIA Portal, FC 84 is not carried forward as a named block. The native STEP 7 integer-division instruction /I produces identical arithmetic but exposes the result through the Status Word (STW / STATUS) instead of dedicated boolean outputs. This article maps every FC 84 parameter to its STEP 7 equivalent and shows how to recover the missing boolean flags using jump instructions evaluated on the status word.

The procedure applies to CPU firmware families that support the STL /I operation, i.e., S7-300 (CPU 312/314/315/317/319) and S7-400 (CPU 412/414/416/417) running STEP 7 V5.x or TIA Portal with active STL language switching. Reference the official Siemens migration manual STEP 7 - From S5 to S7 (entry ID 45531547) for the broader conversion ruleset.

Prerequisites

• STEP 7 V5.5 SPx or TIA Portal V13+ with the STL editor enabled (Options > Package management > STL).
• S7-300/S7-400 CPU whose firmware supports the /I instruction (standard for all S7-CPU since CPU 312 IFM).
• Source S5 program with the original CALL FC 84 block instance and a documented I/O parameter list (Z_1, Z_2, OV, FEH, Z3_0, Z4_0, Z_3, Z_4).
• Free bit memory (M area) and word memory (MW) range that does not collide with the existing S7 symbol table. Reserve eight consecutive flags for the recovered status outputs (e.g., M 50.0–M 50.7).
• Optional: the Siemens S5-to-S7 Converter tool (entry 45531547) to perform the bulk block conversion; this guide covers only the manual replacement of FC 84.

FC 84 Parameter Mapping

The S5 FC 84 interface uses formal parameters beginning with Z (German: Zaehler = dividend/quotient). The following table lists each parameter, its data width, meaning, and the STEP 7 equivalent after conversion.

STEP 7 /I Instruction Behavior

The STEP 7 integer-division instruction /I consumes two 16-bit operands previously loaded into the two accumulators. The 32-bit subtraction chain that produces the quotient is documented in the Siemens S5-to-S7 conversion manual section 4.7 ("Arithmetic Functions"). The resulting distribution in the 32-bit accumulators is:

Use T MD <tag> to deposit both words into one double-word marker; the even MW receives the remainder and the odd MW receives the quotient on S7-300/400. The layout is little-endian within ACCU1, which matches the byte order of T MD.

Status Word Reference

The S7 status word (STW) is a 16-bit register updated by every arithmetic, comparison, and word logic instruction. After /I, the relevant bits hold the same diagnostic information that S5 FC 84 returned as discrete flags.

After /I, the four CC/OV combinations decode to the FC84 outputs as follows:

Step-by-Step Conversion

1. Load the divisor first, then the dividend. STEP 7 pops ACCU1 into ACCU2 on each L, so the divisor must be loaded first to satisfy the ACCU2 ÷ ACCU1 semantics of /I.

       L     MW 104          // divisor Z_2 (from DB22.DBW...)
       L     MW 122          // dividend Z_1
       /I                     // 16-bit signed integer division
       T     MD 124          // MD124: MW126 = remainder (Z_4), MW124 = quotient (Z_3)
   

2. Reset the four FC84 boolean outputs before evaluating. Use CLR to clear RLO, then assign zero to each flag.

       CLR
       =     M 50.1          // OV
       =     M 50.2          // FEH (div/0)
       =     M 50.3          // Z3_0 (quotient zero)
       =     M 50.5          // Z4_0 (remainder zero)
   

3. Detect division by zero via JUO. The combined condition (CC1=1 AND CC0=1) flags an invalid operation, which on integer division means divisor = 0.

       JUO   DIV0            // CC1=1 & CC0=1 → jump to DIV0 handler
       JU    OK              // else continue with OK branch
   DIV0: SET
       =     M 50.2          // FEH = 1
       =     M 50.1          // OV = 1
       BEU                   // block end unconditional; skip quotient-zero test
   OK:
   

4. Detect quotient-zero via JZ.

       JZ    Q0              // CC0=1 & CC1=0 → quotient = 0
       JU    QNZ
   Q0:  SET
       =     M 50.3          // Z3_0 = 1
   QNZ:
   

5. Detect remainder-zero by direct comparison. Because the remainder is held in MW 126 (high word of MD 124), compare it with zero and set the flag.

       L     MW 126
       L     0
       ==I
       =     M 50.5          // Z4_0 = 1 if remainder equals zero
   

6. Latch overflow using OS for cross-scan visibility.

       JO    OVF             // OV=1 (also true on div/0 – already handled)
       JU    NOV
   OVF: SET
       =     M 50.1          // OV latch
   NOV:
       JOS   OSR             // clear stored overflow after reading
   OSR: NOP 0
   

7. Continue with the original downstream logic. Both Z_3 (MW 124) and Z_4 (MW 126) are valid integers; consume them in place of the S5 call result.

Complete STL Snippet

// --- Replace S5: CALL FC 84 (Z1=MW122, Z2=MW104, ...) ---
// Reset FC84 boolean outputs
      CLR
      =     M 50.1          // OV
      =     M 50.2          // FEH (div/0)
      =     M 50.3          // Z3_0
      =     M 50.5          // Z4_0

// Load and divide
      L     MW 104          // divisor Z_2
      L     MW 122          // dividend Z_1
      /I                     // 16-bit signed integer division
      T     MD 124          // MW126 remainder, MW124 quotient

// Division-by-zero check (CC1=1, CC0=1)
      JUO   DIV0
      JU    OK
DIV0: SET
      =     M 50.2          // FEH = 1
      =     M 50.1          // OV = 1
      BEU

// Quotient-zero check (CC0=1, CC1=0)
OK:   JZ    QZ
      JU    QNZ
QZ:   SET
      =     M 50.3          // Z3_0 = 1

// Remainder-zero check (direct compare)
QNZ:  L     MW 126
      L     0
      ==I
      =     M 50.5          // Z4_0 = 1

// Read and clear stored overflow
      JOS   OSR
OSR:  NOP   0
// --- End replacement; downstream logic continues with MW124/MW126 ---

Reading the Status Word Programmatically

If you prefer to inspect the entire status word symbolically rather than rely on individual jump instructions, load the STW into accumulator 1 with L STW and mask the desired bits. The mapping from FC84 output to STW bit is:

For full word access, use:

      L     STW             // load 16-bit status word
      T     MW 200          // local copy for inspection
      L     MW 200
      L     W#16#0020       // OV mask
      UW
      L     W#16#0020
      ==I
      =     M 50.1          // OV recovered

Block Errors (FB 238–FB 251) After Bulk Conversion

When STEP 7's converter (or the S5-to-S7 tool) processes an S5 program, S5-specific standard function blocks such as FB 238 through FB 251 (analog value handling, PID, and integrator blocks in the S5-135U/155U libraries) are flagged as "not convertible". The online error "Error from FB 238 to FB 251" indicates that the converter could not auto-generate the S7 equivalents. Manual remediation:

1. Delete the unresolved FB 238–FB 251 calls from the S7 STL source.
2. Replace them with the corresponding S7 standard library blocks: FB 41 (CONT_C, continuous PID), FB 42 (CONT_S, step PID), FB 43 (PULSEGEN), FC 106 (UNSCALE), FC 105 (SCALE).
3. Recompile and download the S7 program. Refer to Siemens entry ID 45531547 for the cross-reference table.

Verification

Validate the conversion on the target CPU using the STEP 7 Monitor/Modify function or PLCSIM:

1. Force MW 122 = 12345, MW 104 = 0. Run one OB1 cycle. Expect M 50.2 = 1 (FEH), M 50.1 = 1 (OV), MW 124 = 0, MW 126 = 0.
2. Force MW 122 = 100, MW 104 = 7. Expect MW 124 = 14 (quotient), MW 126 = 2 (remainder), M 50.3 = 0, M 50.5 = 0.
3. Force MW 122 = 0, MW 104 = 55. Expect MW 124 = 0, MW 126 = 0, M 50.3 = 1, M 50.5 = 1.
4. Force MW 122 = -100, MW 104 = 7. Expect MW 124 = -14, MW 126 = -2, M 50.3 = 0, M 50.5 = 0, CC1 = 1.
5. Cross-check with PLCSIM breakpoint on the /I line to inspect ACCU1 (quotient/remainder) and the status word bits.

Troubleshooting Matrix

Notes on TIA Portal

In TIA Portal, the SCL text editor treats integer division as / and modulo as MOD. The compiler does not expose CC0/CC1 directly; instead, you must branch on the result:

#quotient  := #dividend / #divisor;        // raises exception on div/0
#remainder := #dividend MOD #divisor;
IF #quotient = 0 THEN #z3_0 := TRUE; END_IF;
IF #remainder = 0 THEN #z4_0 := TRUE; END_IF;

Wrap the division in an IF #divisor <> 0 THEN guard to replicate the FC84 FEH behavior without relying on the OB121 error handler.

FAQ