Resetting S7 Timers in STL: Controlling T0 and M5.0 with I0.0

Overview

This reference explains how to stop a Siemens SIMATIC S7-300/S7-400 on-delay timer (T0) and reset a flag (M5.0) in Statement List (STL / AWL) when the initiating input I0.0 returns to logic 0. The original program uses SD (Start On-Delay Timer as a level-triggered load), which in the S7 instruction set only loads the time value and starts the timer while RLO=1; once loaded, the timer continues to run for the remaining duration even if I0.0 drops out, because the elapsed-time value is retained in the timer's internal word. The fix is to use the R (Reset) instruction on both T0 and M5.0 in a network that executes when I0.0 = 0, and to convert the trigger from a level to a controlled start/stop pattern.

The example uses the standard S7-300 bit, byte, and word memory areas: I0.0 (input), M5.0, M5.1 (flags), MB30 (flag byte), and T0 (timer word). The S5T#10S format is a SIMATIC S5-compatible time constant that loads 10 seconds into the timer's accumulator. The corrected STL pattern is fully compatible with STEP 7 V5.x and the S7-300/S7-400 instruction set as documented in the SIMATIC S7-300/400 Statement List (STL) Programming Manual.

Prerequisites

• STEP 7 V5.5 or higher with the S7-300/S7-400 CPU support package installed (CPU firmware 2.x or 3.x for S7-314/315/317/319; CPU 318-2 DP/PN works identically).
• Knowledge of the STL (AWL) editor in SIMATIC Manager: File > Open > LAD/FBD/STL Editor.
• Familiarity with RLO (Result of Logic Operation), the implicit accumulator pair ACCU1/ACCU2, and status word bits BR, CC0, CC1, OV, OS, OR, STA, RLO, and /FC.
• Hardware wiring of I0.0 to a 24 V DC source (input byte 0 of the S7-300 SM321 DI module), and a digital output wired to drive a load if T0/M5.0 are to control something physical. The patterns below are pure logic and run with no external hardware.

Understanding S7 Timer Behavior in STL

The S7 instruction set defines five timer instructions. Each is a single STL operation that acts on the timer word (16 bits) and the timer bit (a single bit in the process-image or flag area).

The crucial point is that SD (Start On-Delay as level) does not stop the timer when the input goes low. It only loads the time value S5T#10S into the timer's internal word and starts the down-counter while RLO = 1. When RLO returns to 0, the timer bit T0 returns to 0 (because the time has not yet elapsed), but the time value TW in the timer word is not automatically cleared. The next time RLO rises, the load is repeated. This is why the original code "continues" the timer — it never actually stops; it just appears to idle.

To force a stop, the engineer must issue a reset. The R instruction on a timer word performs three things atomically when RLO = 1: it sets the timer bit to 0, it clears the elapsed-time value (sets it to 0), and it clears the internal state. This is the only STL mechanism that produces a defined stopped state for SD and SS timers.

S5T Time Format Specification

The S5 time format is a 16-bit BCD value with a 4-bit time base and a 12-bit time value. It is a legacy format inherited from SIMATIC S5 and remains fully supported in S7-300/S7-400 STL.

STEP 7 automatically selects the time base when the user enters a value. For S5T#10S, the time base is 10 (1 s) and the BCD value is 1 0010. For S5T#5M30S, the time base is 10 (1 s) and the BCD value is 5 30. For sub-second precision use the IEC time format T#5s300ms (S7-400 / S7-300 with CPU 3xx PN/DP).

Root Cause of the Original Behavior

The original STL block contains the following sequence (excerpted and normalized for clarity):

//  Network 1: detect MB30 == 0
A     I0.0
JCN   M03        // if I0.0 = 0, jump to M03 (skip everything)
L     B#16#0
L     MB30
==I              // ACCU2 == ACCU1  (MB30 == 0?)
=     M5.0       // set M5.0 if MB30 == 0

//  Network 2: detect MB30 == 1 and start timer
A     M5.0
JC    M01
M01: L     B#16#1
T     MB30
JC    M02
M02: L     B#16#1
L     MB30
==I              // MB30 == 1?
=     M5.1
A     M5.1
L     S5T#10S
SD    T0         // start on-delay, runs as long as RLO = 1

A     T0
BEC              // block end conditional

Three issues cause the timer to keep running after I0.0 returns to 0:

1. No explicit reset path. When I0.0 drops, the JCN M03 jumps over the SD instruction, but the timer's time value is not cleared. On the next SD load, the timer resumes from wherever it was, not from 10 s.
2. Use of ==I with side-effects. The L MB30 / ==I pattern overwrites the RLO of the previous AND, which is poor practice and can mask rising edges. A clean STL implementation separates the comparison result (in BR) from the AND-stack.
3. BEC before a label. BEC (Block End Conditional) returns from the current FB/FC when RLO=1. The T0 state is preserved in the timer word, so a subsequent scan cycle with I0.0 = 1 will see a partially elapsed timer.

Step-by-Step: Corrected STL Implementation

The corrected logic below uses three networks: a reset network (runs when I0.0 is OFF), a start-and-monitor network (runs when I0.0 is ON), and a status-mirror network (exposes MB30 to DB208.DBX0.0 as the original program requires). It also uses an edge flag M5.2 to ensure the timer is started only on a rising edge of I0.0 — which is the canonical S7-300/400 pattern for a one-shot timer trigger.

Network 1 — Reset Timer and Flags on Falling Edge of I0.0

//  Reset T0, M5.0, M5.1, M5.2 when I0.0 is OFF
AN    I0.0           // RLO = 1 if I0.0 = 0
R     T0             // reset timer word: bit=0, time=0
R     M5.0
R     M5.1
R     M5.2
BEC                  // optional: if used inside an FC, return

The AN I0.0 instruction (AND-NOT) produces RLO=1 exactly when I0.0=0. The subsequent R instructions are conditional: they execute only when RLO=1. This is the inverse of the start network and guarantees a defined stopped state. The reset of M5.2 (the edge memory bit) is also important to prevent a stale edge from triggering the timer on the next rising edge of I0.0.

Network 2 — Start Timer on Rising Edge of I0.0

//  Start on-delay T0 for 10 s on the rising edge of I0.0
A     I0.0
FP    M5.2           // positive edge: RLO=1 only for one scan on 0->1
L     S5T#10S
SD    T0

FP M5.2 (Flanke Positiv / Positive Edge) tests the current RLO against the previous RLO stored in the edge bit address M5.2. The output RLO is 1 for exactly one OB1 scan cycle on every 0→1 transition of I0.0. The SD then loads the time value and starts the timer. Because the trigger is now edge-based rather than level-based, the timer will not "keep running" if I0.0 stays high; it will simply reload on every rising edge. If the engineer wants a strict one-shot that ignores re-triggers while running, see Network 3 alternative below.

Network 3 — Monitor and Latch M5.0 After 10 s Elapsed

//  Latch M5.0 while timer is running AND MB30 = 0 (precondition for state DB208.DBX0.0)
A     T0
L     B#16#0
L     MB30
==I
A     T0
S     M5.0           // set M5.0 latched

//  Latch DB208.DBX0.0 when MB30 = 0
A(
L     0
L     MB30
==I
)
=     DB208.DBX0.0

This network uses the timer bit T0 directly (it is 1 while the on-delay is counting and goes 0 when elapsed, or is reset). The S M5.0 latches the flag. M5.0 is cleared only by the R M5.0 in Network 1 (when I0.0 drops), giving the engineer a clean on/off control surface.

Alternative: Strict One-Shot Timer (Ignores Re-Trigger While Running)

//  Network 2-alt: start only if T0 is not already running
A     I0.0
AN    T0              // AND-NOT: RLO=1 only if I0.0=1 AND T0=0
FP    M5.2
L     S5T#10S
SD    T0

This prevents the engineer from re-loading the timer mid-count. Add a similar AN M5.0 if the application requires the start input to be ignored while the output flag is latched.

Timer Instruction Reference

The timer's elapsed time is read in two ways: the bit T0 gives a boolean indication, and the time value can be read with L T0 (load timer word into ACCU1 as BCD). The time word can also be output directly to the process image; for example, an OUT T0 in the symbol table maps the 16 bits to output word 0 of the configured slot. See the SIMATIC S7-300/400 STL Programming Manual section on "Timer Instructions" for the full bit layout and scan-cycle behavior.

Comparison: Level-Triggered vs Edge-Triggered Timer Control

Verification

1. Open the STL editor with the corrected program and download the block (FB/FC) to the CPU using PLC > Download in SIMATIC Manager. Ensure the CPU is in STOP or RUN-P mode.
2. Monitor in online mode. Open the block in Debug > Monitor (Ctrl+F7). Observe the green RLO column. With I0.0 = 0, Network 1 should show RLO = 1 on AN I0.0 and 1 on each R instruction. The timer bit T0 should be 0 (red).
3. Force I0.0 = 1 using a test switch or the VAT table (Monitor/Modify > Force). The FP M5.2 line should pulse RLO = 1 for one OB1 cycle (typically 10–100 ms depending on cycle time). The SD line should show RLO = 1 momentarily, and the timer bit T0 should rise immediately.
4. Observe the elapsed time in the VAT table. Open a VAT, type T0 in the address column and format it as "TIMER (S5TIME/BCD)". The value should count down from 10 s. If it does not, check that the time base field (bits 12–13) reads binary 10 (1 s) for S5T#10S.
5. Release I0.0. Within one OB1 scan, T0 must drop to 0 and M5.0 must clear. Use the VAT Modify function to confirm by writing 0 to T0 and M5.0 and verifying the result.
6. Repeat the cycle five times to ensure deterministic behavior. Check the diagnostic buffer (PLC > Diagnostic Buffer) for any CPU STOP transitions or OB1 cycle-time overruns (event ID 0x3502, 0x3503, 0x3504 for cycle-time fault on CPU 315-2 PN/DP).
7. Validate with a second edge re-trigger: pulse I0.0 on/off/on/off rapidly (period < 1 s) and confirm that T0 and M5.0 toggle in the expected pattern. If the application requires no re-trigger during the run, use the alternative one-shot pattern above.

Common Pitfalls and Edge Cases

• Forgetting to reset M5.0 on startup. In a warm restart (OB100) the flag area is non-retentive only if declared so. Add R M5.0, R M5.1, R M5.2 in OB100 to guarantee a clean slate. See SIMATIC S7-300 CPU 31xC and CPU 31x: Technical Data for retentive-area configuration.
• Using the timer bit T0 as both an input and an output. The A T0 in the original program queries the bit, but it is also the timer's running flag. If the same T0 is used as an interlock elsewhere, the engineer may get a feedback loop. Use separate flags for the running state and the output state.
• S5T rounding. S5T#7S is stored with a 1 s time base, so any value below 10 s rounds to the nearest 1 s. For 100 ms precision, use S5T#1S and then re-trigger, or use IEC timer format T#7s300ms in SCL/ST with TON / TP / TOF from the IEC 61131-3 standard library.
• OB1 cycle time > timer period. If the OB1 cycle time exceeds the timer duration, the timer will be loaded multiple times during a single user-program scan. Use OB35 (cyclic interrupt at 100 ms default) for precise timer operation, or break the loop with an intermediate flag.
• Using L T0 (load time) inside a comparison. The value loaded is the S5T BCD format, not an integer. To compare against an integer, use LC T0 to load the value in BCD, then ITD / BTI to convert, or use the IEC TON with ET (elapsed time) of type TIME (DInt).
• JCN/JC labels must be unique per block. The original code uses M01, M02, M03 — these are valid local labels. The colon : is required and the label must be the first token of the line.
• Retentive behavior on S7-300 vs S7-400. The CPU 314, 315, 317 default to a specific retentive-timer range; the S7-400 defaults differ. Verify the hardware configuration in HW Config > CPU Properties > Retentive Memory. If T0 is in the retentive range, a power cycle preserves the elapsed time, which can re-trigger the output unexpectedly. Move the timer out of the retentive range, or issue R T0 in OB100.

Diagnostic Tools and Cross-References

• VAT (Variable Table): Insert > S7 Block > Variable Table. Type T0 and MW5 to monitor the timer word and the flags M5.0 and M5.1 simultaneously. Set the display format to "TIMER (BCD)" for T0 and "BINARY" for the flag byte.
• Status in the STL editor (Ctrl+F7) shows RLO, STA, and the accumulator values in real time. Use this to confirm whether FP M5.2 actually fires on the rising edge of I0.0.
• Cross-reference (Options > Cross-Reference): lists every use of T0, M5.0, MB30 in the S7 program. Use this to find the source of any unwanted reset of the flag or timer.
• Stack list in the diagnostic buffer (open with PLC > Diagnostic/Setting > Diagnostic Buffer). After a CPU STOP, the stack list shows the OB1 line and the RLO at the point of fault.
• Reference materials: SIMATIC S7-300/400 Statement List (STL) Programming Manual (45523465), SIMATIC S7-300 CPU 31xC Technical Data (45523810), S7 F/FH Systems Configuring and Programming (1176940), and the IEC 61131-3 standard for the timer instruction semantics.

Field-Commissioning Checklist

1. Wire I0.0 to a 24 V DC test switch. Confirm the input LED on the SM321 module lights when the switch is closed.
2. Download the corrected FB/FC to the CPU. Verify the CPU is in RUN (green RUN LED solid, no SF/BF red LEDs).
3. Open the VAT and force I0.0 = 1. Confirm T0 starts counting down from 10 s and the timer bit T0 rises immediately.
4. After 10 s, confirm DB208.DBX0.0 reflects the correct state (should be 1 when MB30 = 0, 0 when MB30 = 1).
5. Drop I0.0 to 0. Confirm T0 and M5.0 both go to 0 within one OB1 scan.
6. Cycle the power (cold restart). Confirm the behavior is identical to step 3–5 with no residual state.
7. Document the wiring, the timer part number (S7-300 6ES7 313-6CG04-0AB0, or whatever CPU is in service), and the STEP 7 version (V5.5 SP4 or V5.6) in the project documentation.