Resolving DP/AS-i Link Advanced I/O Address Mismatch in STEP 7

Problem Description

A Siemens S7-400 station with an AS-i Link Advanced module (order number 6GK1 415-2BA20) on PROFIBUS-DP exhibits a digital I/O address shift after the Adopt Actual → Desired (German: Ist → Soll übernehmen) command is executed in the AS-i Master diagnostics dialog. The configuration that was downloaded into the CPU still maps slave 1A to input byte 801, but the re-uploaded hardware configuration returns slave 1A at input byte 800 with slave 1B shifted to 816. The PLC program continues to operate against the addresses that were downloaded, so a write to output 1A physically energises output 3A — a silent, dangerous mapping error that can only be detected by visual inspection of the valve manifold or by cross-referencing the AS-i diagnostic frame.

The affected stack is:

• CPU: SIMATIC S7-400 (any 41x / 416 / 417 / 41xH)
• DP Master: PROFIBUS interface of the S7-400 (e.g. 6GK7 443-1EX11)
• DP/AS-i Gateway: DP/AS-i Link Advanced 6GK1 415-2BA20, firmware V2.1
• Engineering: STEP 7 V5.4 + SP4 (or earlier SP)
• Slaves: AS-i A/B slaves on two AS-i lines per gateway (1M = Line 1, 2M = Line 2)

The bus cycle appears healthy (no DP diagnostics, no AS-i CER code 0x0F / 0x1F), which makes the fault particularly misleading.

Observed Symptom: Download vs. Upload Address Map

The two tables below are taken from a real session. The downloaded map reflects what the project was compiled to ship. The uploaded map is what HW Config → Station → Upload to PG reads back from the CPU after Adopt Actual → Desired has been triggered. Address bytes are decimals; bit offsets are added in the editor.

Downloaded configuration (intended)

Uploaded configuration after Adopt Actual → Desired

The mapping is no longer monotonic. Outputs now collide: writing PQB 801 energises slaves 1A and 3A simultaneously because the B-slaves have been re-allocated to the upper 816..818 byte block.

Root Cause: STEP 7 V5.4 Object Manager Defect

Siemens documented a limiting condition in the STEP 7 Object Manager used to build the DP/AS-i Link Advanced slot frame. The Object Manager builds the AS-i slot list in two passes: once during the initial Download to Target System (where it uses the project source) and once during any subsequent Upload from Target System (where it re-interprets the AS-i master’s live slave list). When spare slaves are configured but not physically present, the live list triggers the Adopt Actual → Desired workflow, which causes the second pass to reassign the I/O offset table. With STEP 7 V5.4 base, SP1, SP2, SP3 and SP4 the slot offset for AS-i Line 1A is computed incorrectly whenever the upper B-slave row of the previous line was previously marked as Spare in the project.

This is purely an engineering-tool defect — the PLC program stored in the CPU retains the original, correct mapping until the project is rebuilt against the uploaded (corrupted) configuration and re-downloaded. The AS-i master firmware V2.1 itself is not at fault.

Why the Project Code Does Not Match the Uploaded Config

1. Download path. STEP 7 compiles the HW Config into the System Data Blocks (SDB) of the project and pushes them to the CPU. The CPU’s SDBs reflect the engineering intent (table 1).
2. Spare-slave alarm. Because the project declares spare B-slaves that are not physically connected, the AS-i master raises System Fault (SF) and Configuration Error (CER) on the Link Advanced front panel.
3. Adopt Actual → Desired. Selecting this button rewrites the AS-i master’s internal desired configuration (LCS list 1) to match the actual configuration (LCS list 0). It does not touch the CPU’s SDBs.
4. Upload path. When HW Config re-reads the station from the CPU it queries the AS-i master for the new LCS list 1. The corrupted Object Manager code interprets the reordered LCS list and re-assigns offsets incorrectly, producing the table 2 mapping.
5. Net effect. The CPU continues to execute the original program against the original offsets, but the engineering view (uploaded HW Config) shows a different map. Re-downloading the uploaded project would propagate the corruption into the running CPU.

Solution

Step 1 — Capture the working configuration

1. In SIMATIC Manager, mark the S7-400 station and choose PLC → Save Service Data (Snapshot). Save the ZIP to a project archive directory.
2. Export the AS-i line diagnostics with AS-i Master → Diagnostics → Save as CSV so the LCS list 0 (actual) and LCS list 1 (desired) of each line are recorded.
3. Do not save the uploaded HW Config — it is contaminated.

Step 2 — Install STEP 7 V5.4 Service Pack 5

1. Close SIMATIC Manager and any STEP 7 add-ins.
2. Run the installer for STEP 7 V5.4 SP5 (delivered as STEP7_V54_SP5.exe). The SP requires administrator rights and a clean registry snapshot. Existing projects are preserved.
3. Reboot. Verify Help → About → Installed Software shows STEP 7 V5.4 + SP5 / K5.4.5.0.

Step 3 — Recompile the HW Config

1. Open the station in HW Config on the patched tool.
2. Without changing any slot or address, choose Station → Consistency Check then Save and Compile. The rebuilt SDBs now contain the fixed Object Manager code paths.
3. Download to the target CPU. Do not first perform Upload from Target — start from the engineering source.

Step 4 — Resolve the SF / CER alarms correctly

Instead of running Adopt Actual → Desired against a configuration that contains spares, choose one of the two supported strategies:

Step 5 — Verification (mandatory)

1. Open a watch table with VAT_1 containing all configured Q addresses from byte 800 onward, e.g.:

   // Watch table — force one output per AS-i B-slave row
   QW 800    // Line 1A area, bit pattern 0x0001 — should light Slave 1A
   QW 802    // Line 2A area, bit pattern 0x0001 — should light Slave 2A
   QW 803    // Line 3A area
   QW 804    // Line 4A area
   …
   QW 810    // Line 10A area
   

2. Set the CPU to STOP, force each value to 0x0001, switch to RUN-P, and visually verify on the valve manifold that only the corresponding solenoid LED lights.
3. Re-upload HW Config and confirm byte-for-byte parity with table 1.

Verification Matrix

Edge Cases and Field Notes

• Mixed firmware on the Link Advanced. The defect is in the STEP 7 Object Manager, not in firmware V2.1. Sites that have the AS-i master firmware at V1.x or V2.0 still see the symptom, because the engineering tool is the source of the corrupted slot list.
• More than two AS-i lines. The 6GK1 415-2BA20 only supports two AS-i lines, but the symptom also occurs if the project accidentally declares a third "ghost" line during slot reassignment. Remove the ghost line in HW Config before recompiling.
• Migration to TIA Portal. The DP/AS-i Link Advanced is also represented in the TIA Portal V13+ hardware catalog under Configuring an AS-i master and slave device. Sites planning a migration should re-import the S7-400 project into TIA Portal only after the STEP 7 V5.4 SP5 patch is installed, otherwise the corrupted slot table is carried over.
• S7-400H redundant CPUs. Both CPUs must be patched to the same STEP 7 version. Inconsistency between H-CPU engineering stations has been observed to introduce an additional 1-byte offset during SDB resynchronisation.
• CPU 410 vs. S7-400 classic. The SIMATIC S7-400 CPU 410 (process automation) requires STEP 7 V5.4 SP5 or V5.5; V5.4 base refuses to compile the CPU 410 rack.

Why You Should Never Adopt the Uploaded Configuration

A common temptation after seeing the corrupted uploaded view is to "make it match" by editing the project to match the uploaded table. Do not do this: it permanently bakes the bug into the project source. The upload view is wrong; the engineering source is right (provided STEP 7 V5.4 SP5 is installed and the project was last saved in a clean state). Always debug from the engineering source downward — never from the upload upward.

Related Manuals and References

• SIMATIC DP/AS-i Link Advanced (6GK1 415-2BA20) product page
• STEP 7 V5.4 Service Pack 5 download entry
• Configuring an AS-i master and slave device (TIA Portal manual)
• SIMATIC S7-400 Automation System manual
• AS-Interface System Description

Frequently Asked Questions