Resolving Siemens TIA Portal V15 DB Offset Shift After STEP 7 V5.6 Migration
Migrating a STEP 7 V5.6 project into TIA Portal V15 typically preserves the program logic, the symbol table, and the data block layout. However, certain UDTs (User-Defined Data Types) can change their internal byte alignment during the conversion, which shifts every absolute address that follows the UDT by several bytes. A common field symptom is exactly the one reported in the original case: a STEP 7 V5.6 tag at DB2.DBX216.0 (initial step of an S7-Graph sequencer) appears at DB2.DBX211.0 once the project has been converted into TIA Portal V15. The 5-byte delta is the signature of a UDT alignment change, not a hardware fault and not a configuration loss.
This reference documents the underlying cause, the diagnostic workflow inside the TIA Portal migration log, and the corrective actions available for both the symbolic and the absolute addressing paths.
1. Problem Summary
| Parameter | STEP 7 V5.6 | TIA Portal V15 |
|---|---|---|
| Target CPU | S7-300 / S7-400 family | S7-300 / S7-400 / S7-1500 (depending on the converted target) |
| DB number | DB2 | DB2 |
| Symbolic access | Enabled (user reports symbolic use) | Preserved symbolically but absolute address shifted |
| Initial step bit | DB2.DBX216.0 | DB2.DBX211.0 |
| Bit offset delta | — | -5 bytes (216 - 211 = 5) |
| Suspect UDT |
GraphTransition UDT (S7-Graph) |
GraphTransition UDT now 16 bytes in TIA Portal |
The 5-byte negative shift on the initial step address is the most important number in the diagnostic: it rules out a generic data block re-numbering, and points instead at a change inside a UDT that lives upstream of bit 216.
2. Root Cause: UDT Alignment and Optimized Block Access
Two structural changes in TIA Portal affect UDT byte layout:
- Optimized block access (also called "Symbolic access only") was introduced with S7-1500 and is also available for S7-300/400 in TIA Portal V15. With optimization enabled, the compiler is allowed to reorder UDT elements and to insert alignment padding. With optimization disabled, the layout remains strict byte-by-byte compatible with STEP 7 V5.6.
-
UDT element alignment follows the natural alignment rule:
WORDon even byte offsets,DWORDon offsets divisible by 4,LREAL/LWORDon offsets divisible by 8. STEP 7 V5.6 historically packed UDTs more tightly for S7-300/400. When the same UDT is converted and the editor allows alignment padding, members are realigned, and the total length grows.
In the reported case, the GraphTransition UDT (the type S7-Graph uses for the step/transition control structure) was approximately 11 bytes in STEP 7 V5.6 and is 16 bytes in TIA Portal V15. The 5-byte growth pushes every absolute bit access downstream of the UDT down by 5 bytes, producing exactly the observed shift from DBX216.0 to DBX211.0.
DBx.DBBy.z access to the affected range are exposed.
3. Diagnostic Workflow
Before applying any fix, confirm the cause via the TIA Portal migration log and a UDT layout comparison.
3.1 Open the Migration Log
- In the TIA Portal project tree, expand Common data.
- Open the Logs folder.
- Double-click the most recent
.xmllog file. The log opens in the work area. - Filter for entries tagged
UDT,DB, orGraph.
The migration log records every block conversion that required intervention, including UDT realignment notices and warnings about absolute addressing. Refer to the TIA Portal V15 online help, TIA Portal V15 - Commissioning and Programming, section "Project migration", for the full structure of this log file.
3.2 Compare UDT Lengths
- In STEP 7 V5.6, right-click the
GraphTransitionUDT and open its properties. Note the Length in bytes. - In TIA Portal V15, navigate to PLC data types, open the same UDT, and note its new length.
- Compute the delta. A 5-byte delta on a UDT located immediately upstream of the affected address is the expected fingerprint for this fault.
3.3 Identify Affected Tags
Use a global cross-reference to find every absolute access to the shifted address range:
- In the TIA Portal project, select the program blocks folder.
- Open the Cross-reference editor (menu Tools → Cross-reference, or the icon in the toolbar).
- Filter the address column for
DB2.DBX216.0and for all addresses inside the suspected UDT length range, e.g.DB2.DBX200.0throughDB2.DBX220.0. - For every match, note the using block, network, and operand.
The cross-reference tool is documented in the TIA Portal V15 help portal under "Cross-references and go to".
4. Solution Options
Three remediation paths are available. Choose the path that matches the coding standard used in your project.
4.1 Preferred Solution: Convert Absolute Addresses to Symbolic
If the original STEP 7 V5.6 program uses symbolic tags everywhere except for the few absolute accesses, replace the absolutes with the symbolic names that were preserved during migration.
- Open the DB2 declaration in TIA Portal V15 and confirm the symbolic name of the "initial step" tag (typically
S_NO,S_INIT, or a project-specific symbol). - In every using block, replace
DB2.DBX211.0with the symbol, for example:
Before (absolute):
A DB2.DBX211.0 // initial step bit
= M 100.0
After (symbolic):
A "DB_Graph".Initial_Step
= M 100.0
This change is stable across future TIA Portal upgrades because symbolic access is independent of the underlying UDT layout. It is also the recommended coding style in the S7-1500 programming guideline (see Siemens Support Entry 90857140 - S7-1500 programming style guide).
4.2 Compensating Update of Absolute Addresses
When the project must remain on absolute addressing (older S7-300/400 maintenance tasks where the symbol table was lost or never populated), subtract the UDT growth delta from every absolute address in the affected range.
General formula for the corrected byte offset:
Offset_TIA = Offset_S5 - (UDT_Length_TIA - UDT_Length_S5)
For the reported case:
Offset_TIA = 216 - (16 - 11) = 216 - 5 = 211
Apply a project-wide search and replace:
- In the TIA Portal editor, press Ctrl+F to open Find and Replace.
- Enable Regular expression and In all blocks of the project.
- Replace
DB2\.DBX(2[0-1][0-9])\.([0-7])with the corrected range. Manual review is mandatory: each replacement must be verified against the UDT boundaries to avoid corrupting adjacent tags.
4.3 Force Standard Block Access (Disable Optimization)
If the target CPU is an S7-300 or S7-400, you can disable the optimized block access on the converted DB to lock the byte layout back to the STEP 7 V5.6 behavior:
- Right-click the affected DB in the project tree and select Properties.
- Open the Attributes tab.
- Clear the check box Optimized block access (German: Optimierter Bausteinzugriff).
- Recompile the project (menu Program → Compile → Software (rebuild all blocks)).
After recompilation, verify that the absolute offsets match the STEP 7 V5.6 layout. This option is not available for S7-1500 targets, where optimized access is mandatory. See the S7-1500 system manual entry on Siemens Support Entry 59191792 - Differences between standard and optimized data blocks.
5. Step-by-Step Resolution for the Reported Case
- Open the TIA Portal V15 project and navigate to PLC data types.
- Confirm that
GraphTransitionis now 16 bytes (was approximately 11 bytes in STEP 7 V5.6). The 5-byte delta matches the observed address shift. - Open DB2 and locate the symbolic tag for the initial step (typically named by S7-Graph as
S_NOorSTEP_NO). - Open the cross-reference and filter for any remaining
DB2.DBX211.0orDB2.DBX216.0access. Replace each occurrence with the symbolic tag. - If the project is S7-300/400 and the project standard is absolute-only, keep the absolute addresses but use the formula in section 4.2 to shift them.
- Recompile the project: Project tree → right-click the PLC → Compile → Software (rebuild all blocks).
- Download the rebuilt program to the PLC (or to PLCSIM for offline verification).
6. Verification
| Check | Method | Expected Result |
|---|---|---|
| Initial step activation | Watch table on the symbolic tag Initial_Step
|
Goes TRUE within one cycle of the Graph sequencer start |
| UDT length match | DB2 declaration view → "Length in bytes" | Matches the value computed by summing the symbolic member sizes plus alignment padding |
| No absolute access warning | Compile output → Information tab | No warning "Absolute access to optimized DB" |
| Online vs offline comparison | Right-click the PLC → Compare → Online/offline | Equal for program blocks and data blocks |
| Graph sequencer start | Operator panel or HMI tag GR_ACTIVE
|
Transitions from step 0 to the initial step in the first OB1 cycle |
The watch table test is the fastest field check. Add the symbolic tag to a watch table in TIA Portal, connect online, trigger the Graph sequencer start condition, and confirm that the bit transitions within one cycle of OB1.
7. Why the Migration Log Sometimes Looks Empty
The original post notes that the migration log only reports a hardware configuration error and no information about the DB shift. This is expected behavior: TIA Portal does not classify a UDT realignment as a migration warning because the resulting program is internally consistent. The compiler assumes that the user is using symbolic access and therefore does not need to be warned about an absolute address change.
The information about the realignment is still present in the project, but in a different location:
- PLC data types: the UDT length column shows the new value.
- Program blocks → DB properties → Compilation: the optimization flag is recorded.
- Cross-reference: the "Address" column reflects the new byte offset.
For deeper diagnostics on the conversion itself, the original STEP 7 V5.6 project can be re-exported to a STEP 7 V5.7 container and compared block by block against the converted TIA Portal project using the SIMATIC Manager "Compare blocks" tool.
8. Migration Best Practices
- Adopt symbolic addressing throughout the project before migration. This isolates the program from UDT alignment changes and from future compiler upgrades. The recommended convention is described in Siemens Support Entry 90857140.
- Disable optimized block access on every DB that is consumed by an S7-300/400 absolute-access program. Once the project is clean, re-enable optimization selectively only on blocks that are used purely symbolically.
- Avoid mixing absolute and symbolic access on the same DB. TIA Portal V15 issues an "inconsistent access" warning when a DB is configured as optimized but is read or written absolutely from an S7-300/400 code section.
- Document every UDT realignment after migration. Add a project note describing the old length, the new length, and the affected tags so that future maintenance engineers understand why the addresses differ from the original design.
- Run the migrated project through PLCSIM before downloading to a running plant. PLCSIM in TIA Portal V15 (article ID 109751728) reproduces the exact UDT layout that will later run on the physical CPU, so any offset shift shows up as a runtime anomaly on the simulated Graph sequencer.
- Pin the TIA Portal version. Re-migrating a project from V15 into V16 or V17 may shift the same UDT again because each version can update the natural alignment rules. Re-validate after every major TIA Portal upgrade.
9. Related Fault Patterns
| Symptom | Likely Cause | First Diagnostic Step |
|---|---|---|
| Initial step bit does not activate in OB1 | Absolute access to shifted UDT area | Open DB2 in declaration view, check byte offsets against STEP 7 V5.6 reference |
| Compiler warning "Absolute address in optimized DB" | Optimization enabled and absolute access still present | Replace absolute with symbolic OR disable optimization |
| Online/offline comparison shows DB differences | UDT realignment not downloaded | Download the rebuilt blocks to bring the PLC into sync |
| Graph sequencer starts in a different step than expected | Step number tag shifted by UDT alignment | Check S_NO and SWITCH_POS symbols against the expected initial step |
| SF (system fault) LED on CPU after download | Block consistency error from a half-converted DB | Recompile all blocks and re-download in the order: system data, OB, FB, FC, DB |
10. Standards and Reference Documentation
- TIA Portal V15 - Commissioning and Programming (Siemens Support Entry 109751728)
- S7-1500 Programming Style Guide (Siemens Support Entry 90857140)
- Differences Between Standard and Optimized Data Blocks (Siemens Support Entry 59191792)
- Migrating STEP 7 V5.x to TIA Portal (Siemens Support Entry 109763836)
- S7-Graph V15 Configuration and Programming (Siemens Support Entry 109478012)
FAQ
Why did DB2.DBX216.0 in STEP 7 V5.6 become DB2.DBX211.0 in TIA Portal V15?
The 5-byte negative shift is caused by a UDT alignment change. In STEP 7 V5.6 the GraphTransition UDT occupied approximately 11 bytes. In TIA Portal V15 the same UDT, after natural alignment padding, occupies 16 bytes. Every absolute address downstream of the UDT is shifted by the 5-byte growth (216 - 5 = 211).
Is the byte offset change a TIA Portal migration bug?
No. The compiler preserves the declared UDT structure and applies the same alignment rules that S7-1500 already uses. The shift only affects projects that still contain absolute DBx.DBBy.z access. Symbolic access is layout-independent and remains correct.
Can I keep absolute addressing after the migration?
Yes. On S7-300/400 targets, open the DB properties and clear the Optimized block access option to lock the byte layout back to the STEP 7 V5.6 behavior. Then either adjust the absolute addresses manually using the formula Offset_TIA = Offset_S5 - (UDT_Length_TIA - UDT_Length_S5) or leave them unchanged if the DB has been forced back to standard access.
Where can I see which UDT was realigned?
Open PLC data types in the TIA Portal project tree and inspect the Length in bytes column for each UDT. Compare the value with the STEP 7 V5.6 project. The UDT whose length changed is the one that caused the offset shift. The migration log itself does not classify UDT realignment as a warning.
What is the safest way to migrate an S7-Graph project to TIA Portal V15?
Migrate first, then perform a full Online/Offline compare and a Cross-reference review. Replace any remaining absolute access with symbolic tags, run the project through PLCSIM to verify the Graph sequencer start sequence, and only then download to the physical CPU. Re-validate after every major TIA Portal upgrade (V15, V16, V17, V18) because alignment rules can evolve between versions.