Retaining S7-1200 HSC Count Value Through Power Failure

Field engineers using the S7-1200 high-speed counter (HSC) for linear scales, rotary encoders, or flow meters routinely hit one recurring issue: after a power outage, STOP-to-RUN transition, or warm restart, the counter returns to zero. The HSC instance is created, the firmware initializes the input address, and the accumulated position is gone. The fix is to add a retentive global DB as a buffered copy, write the running count into it on every scan, and push that value back to the HSC during the startup OB before the first user program scan touches the counter. This article walks through the exact TIA Portal V11-V18 procedure, the wiring constraints, the CTRL_HSC and High_Speed_Counter instruction parameters, the verification checks, and the field caveats that come from deployed installations.

1. Problem Definition: Why the Counter Resets

The S7-1200 HSC is implemented in the CPU firmware and is not a software counter. The current count value is mirrored into a fixed input (I) address inside the process image. The default allocation, per the TIA Portal online help, places HSC1 at ID1000, HSC2 at ID1002, HSC3 at ID1004, and continues in 4-byte increments up to the maximum number of HSC supported by the CPU. The Siemens documentation states: "The CPU stores the current value of each HSC in an input (I) address."

That I address lives in the process-image input area, which is not backed up by the retentive memory. The HSC instance DB that TIA Portal generates automatically is retentive in some configurations, but the running counter value exposed through the I address is rebuilt from zero on every CPU restart.

Concretely, three conditions wipe the counter:

1. Power-off / power-on (cold restart).
2. STOP-to-RUN transition without power cycle; the HSC is reinitialised when the CPU enters RUN.
3. Reinitialisation of the HSC object in the device configuration, or download of a new hardware configuration.

Marking the HSC instance DB as retentive alone does not preserve the value, because the instance DB only holds configuration metadata, not the live count. The misconception that "HSC retain = automatic backup" comes from confusing the instance DB (configuration) with the I address (live data).

2. HSC Address Map and CPU-Dependent Limits

The default addresses for the current value of each HSC are allocated as follows. They can be changed in the device configuration under "HSC properties" if the I area conflicts with another module.

Maximum input frequency and supported counting modes vary by CPU and by whether the input is an onboard terminal or a signal board (SB) channel. Single-phase maximum is typically 100 kHz on most S7-1200 CPUs, up to 1 MHz on the CPU 1217C onboard inputs, with A/B quadrature rated at 80 percent of the single-phase figure. Refer to the CPU-specific data sheet for the exact rating before sizing the encoder. Counting modes supported by all HSC channels include:

• Single-phase count with internal direction control - one pulse input, direction from program.
• Single-phase count with external direction control - one pulse input, direction from a digital input terminal.
• Two-phase count - two pulse inputs (A and B) where phase relationship encodes direction.
• A/B counter (quadrature) - two pulse inputs with optional Z (zero) reference. Single, double, or quadruple evaluation.
• Frequency measurement - the HSC counts pulses over the period set on the CTRL_HSC PERIOD input.

The control instruction that reads and writes the HSC depends on TIA Portal version:

• CTRL_HSC (legacy, V11 - V18). Compact block, fixed parameter list, supports single and two-phase counting, frequency measurement, and direct write of current and reference values. Documented in the TIA Portal online help under "Legacy CTRL_HSC".
• High_Speed_Counter (V14+). Newer instruction with the same functional role, used in TIA Portal V14 and later projects. Both can coexist in the same project; CTRL_HSC remains supported for backward compatibility.

3. Prerequisites

Before implementing the retain pattern, confirm the following:

• Hardware: S7-1200 CPU with at least one HSC channel wired. Verify the encoder output type (push-pull, totem-pole, 24 V single-ended, or 5 V line driver) matches the input spec; 24 V single-ended encoders need the appropriate digital input filter setting and may require a signal board for the differential HSC inputs on some CPUs.
• Software: TIA Portal V11 SP2 or later. The instructions and configuration paths in this article are valid for V13 SP1, V14, V15, V15.1, V16, V17, and V18. Function blocks written against CTRL_HSC in V11 will compile unchanged in V18.
• Project state: The HSC is enabled in the CPU device configuration. The I address, counting mode, initial value, gate function, and reset behaviour are set. The wiring to the encoder must be in place before commissioning the retain logic; debugging the retain pattern with a floating input wastes hours.
• Retentive memory budget: Each CPU has a fixed amount of bit memory, counters, timers, and DB data that can be marked retentive. The retain budget for a CPU 1214C, for example, is 14 kB. A single DINT for the buffered count uses 4 bytes - well within budget - but multiple HSC channels, recipes, and operator-settable parameters all draw from the same pool. Open the CPU properties, navigate to "Retentive memory", and confirm the projected total is below the CPU limit.

4. Architecture: Buffered Retain Pattern

The retained design has three layers:

1. Live HSC count held in the I address (IDW). Updated by firmware in real time, lost on restart.
2. Retentive shadow DB ("HSC_Retain") in the load memory and work memory with the Retain attribute set. Survives power-off / power-on and STOP-to-RUN.
3. Synchronisation logic in OB1 (write shadow from live) and OB100 (write live from shadow at startup).

On every OB1 cycle, the live count is copied into the shadow DB. On the very first scan after the CPU enters RUN, OB100 pushes the retained shadow value back into the HSC by setting the NEW_CV parameter of CTRL_HSC (or the equivalent input on High_Speed_Counter) and pulsing the NewCV bit. After that, the live count diverges from the shadow as new pulses arrive, and the loop continues. The pattern is sometimes called "save on cycle, load on startup" and is the same architecture used for retentive timers, position counters, and recipe parameter sets.

5. Step-by-Step Implementation

5.1 Create a Retentive Global DB

From the project tree, add a new global DB named "HSC_Retain" with the following structure:

Set the DB's overall retain attribute. In TIA Portal V13 SP1 and later, right-click the DB node, select "Properties", and in the "Attributes" section set "Retain" to "Retain" (S7-1200) or "Memory of retain" (S7-1500, preserved across online download). Per-tag retain is also set in the declaration table's "Retain" column. The "Memory of retain" option for S7-1500 keeps the value across online changes of the program, which is convenient for commissioning but only available on S7-1500. For S7-1200, only the standard "Retain" option is available; an online download that changes the program will reset the retain area unless the user selects "Preserve retentive data" in the download dialog.

5.2 Configure the HSC in Device Configuration

Open the CPU in the device view, select the HSC channel from the navigation tree, and configure:

• Enable: ticked.
• Type: Single phase, two phase, or A/B counter, matching the encoder.
• Count direction: user program controlled, hardware controlled, or both.
• Initial value: 0 (will be overwritten in startup).
• Initial reference value: 0 unless using compare/preset.
• I address: keep the default or remap to avoid conflict with other modules.
• Input filter: minimum supported value for the filter group the HSC terminals belong to.
• Gate function: software gate (controlled by program) or hardware gate (controlled by a digital input). The gate stops counting while inactive; it does not reset the count.

5.3 Insert the HSC Control Instruction

Place a CTRL_HSC block (or High_Speed_Counter for V14+) in OB1. Wire the HSC hardware identifier. The HW_ID is found in the HSC's properties and is typically formatted as "HSC_1" or "CTRL_HSC_1".

CTRL_HSC input parameters relevant to the retain pattern:

CTRL_HSC output parameters:

5.4 Save the Live Count into the Shadow DB

Add the following network in OB1, after the CTRL_HSC call so the current value is fresh:

// OB1 - network: shadow DB update
"HSC_Retain".LastCount := "HSC_Count".CV;       // or use the I address: %ID1000
"HSC_Retain".FirstRunDone := TRUE;
IF NOT "HSC_Retain".LastCountValid THEN
    "HSC_Retain".LastCountValid := TRUE;
END_IF;

The CPU copies the live count from the I address into the retentive DINT on every cycle. After a power cycle, the DB's load memory image is restored, and the last value before the outage is what OB100 will see. The LastCountValid flag is optional but useful: it lets OB100 distinguish a freshly commissioned PLC (where LastCount is 0 because the DB was just initialised) from a PLC that was running and lost power (where LastCount holds a real position).

5.5 Restore the Count in OB100 (Startup)

OB100 executes once after the CPU transitions from STOP to RUN (warm restart). Place the load logic here so the value is in place before OB1's first scan. The HSC is also reinitialised at this point, so a write to NEW_CV is recognised:

// OB100 - network 1: load retained count into HSC
IF "HSC_Retain".LastCountValid THEN
    "HSC_Count".CV := "HSC_Retain".LastCount;
    "HSC_Count".NewCV := TRUE;
ELSE
    "HSC_Count".CV := 0;
    "HSC_Count".NewCV := TRUE;
END_IF;

// OB100 - network 2: log boot time for diagnostics
"HSC_Retain".BootTime := RD_SYS_T;

On the rising edge of NewCV in the first call of CTRL_HSC inside OB100, the CPU writes the CV value into the HSC. Subsequent calls in OB1 must not retrigger the write, because NewCV must see a 0-to-1 transition to act; ensure the network in OB1 does not continuously drive NewCV to 1, otherwise the HSC will reset to the buffered value on every cycle and incoming pulses will be lost.

6. Complete SCL Example (TIA V14+)

The following SCL block can be dropped into any S7-1200 project. Replace the hardware identifier and addresses for your configuration. The block encapsulates the retain logic and can be reused across projects.

FUNCTION_BLOCK "HSC_Retain_Handler"
VAR
    HSC_CV          : DINT;   // live count read from %ID1000 each cycle
    HSC_Shadow      : DINT;   // retentive shadow stored in instance DB
    HSC_Loaded      : BOOL;   // retentive flag: load on next OB100
    HSC_LoadPending : BOOL;   // volatile flag: edge to NewCV
END_VAR
BEGIN
    // 1. read live count from the HSC I area
    #HSC_CV := "HSC_Default".%ID1000;          // default address, HSC1
    // 2. mirror to the retentive shadow every cycle
    #HSC_Shadow := #HSC_CV;
    #HSC_Loaded := TRUE;

    // 3. produce a one-shot NewCV on the cycle following OB100
    IF #HSC_LoadPending THEN
        "HSC_Count".CV    := #HSC_Shadow;
        "HSC_Count".NewCV := TRUE;
        #HSC_LoadPending  := FALSE;
    END_IF;
END_FUNCTION_BLOCK

For the startup load, drop this network in OB100:

// OB100 - executed once on warm restart
"HSC_Retain_Handler".HSC_LoadPending := "HSC_Retain_Handler".HSC_Loaded;
"HSC_Retain_DB".BootTime := RD_SYS_T;

Mark HSC_Shadow and HSC_Loaded as Retain. On every STOP-to-RUN, OB100 fires once, sets HSC_LoadPending, and OB1 pushes the retained value into the HSC on the next cycle. The NewCV pulse is exactly one OB1 cycle wide, so the HSC is loaded once and never overwritten.

7. Counting Mode Details

Each counting mode has a specific implication for retention:

For the Z (zero) reference input on A/B counters, the HSC resets the count to 0 on each pulse of Z. Retention across power-off does not affect Z behaviour, but the post-restart Z pulse will reset the retained count, which is usually what the application wants (homing on power-up).

8. Gate and Reset Behaviour

The HSC has a software gate and, on some configurations, a hardware gate. The gate stops the HSC from counting while inactive; it does not reset the count. Typical patterns:

• Software gate only - the gate is controlled by a program tag. The HSC is enabled while the gate is TRUE. On power cycle, the gate is reinitialised to its default (TRUE unless changed in device config), so the HSC starts counting immediately after OB100 pushes the retained count.
• Hardware gate - a digital input terminal gates the HSC externally. On power cycle, the input must be re-asserted by the field wiring. If the gate is open at startup, the HSC holds the retained value but does not count new pulses. Confirm the gate wiring at commissioning.

Reset behaviour is configured per HSC: an "Initial counter value" reset occurs on a digital input configured as the reset terminal, on a software command, or on the Z pulse of an A/B encoder. The retain pattern does not interfere with the reset; the count is reset to the configured initial value, and OB100 does not push the retained count because the reset has higher priority. If the application must preserve position across an intentional reset, do not use the HSC reset; instead, manage the count in a separate DB and use the HSC purely for pulse counting.

9. Reference Value, Overflow, and Wrap

The HSC reference value (RV) is the threshold for the CV = RV event, which can trigger a hardware interrupt or set a status bit. The reference value is not retained by default; if the application needs a persistent reference, add a DINT in HSC_Retain and load it via the NewRV input on CTRL_HSC in OB100.

Counting range: DINT is signed, covering –2,147,483,648 to 2,147,483,647. A quadrature encoder at 4x evaluation counts 4 per line per revolution. At 10,000 lines per revolution, 4x evaluation, 1,000 RPM, the HSC reaches 4 * 10,000 * 1000 / 60 = 666,666 counts per second. To wrap the full DINT range, the encoder would need to run for about 3,580 seconds (nearly an hour) at that speed, which is not unusual in continuous process machinery. The retention pattern preserves the wrapped value; the application logic must handle the wrap if the range matters. A common technique is to keep a BOOL "Overflowed" in HSC_Retain, set it in OB1 if a wrap is detected, and reset it on homing.

10. TIA Portal Version Compatibility

For new projects on V14+, Siemens recommends High_Speed_Counter. For migration of existing V11-V13 projects, keep CTRL_HSC and the same code will compile and run unchanged. The retain pattern described in this article is identical regardless of the instruction, because the retain logic lives in the application code, not in the instruction.

11. Verification Procedure

1. Online watch: Connect to the CPU, open the HSC_Retain DB, and watch LastCount increment as the encoder turns. Confirm the value updates at the OB1 cycle rate.
2. Power cycle test 1 (no motion): With the encoder stationary, stop the CPU, switch off the 24 V supply for 10 seconds, restore power, and confirm OB100 sets the HSC to the buffered value. The I address should display the pre-outage count. If it displays 0, OB100 is not executing or the HW_ID is wrong.
3. Power cycle test 2 (motion during outage): Mark a known count, switch off, rotate the encoder by N pulses manually, switch back on, and confirm the count has increased by N. If the count is unchanged, the shadow DB is not being updated each cycle, or the retain attribute is missing on the DB tag.
4. STOP-to-RUN test: Toggle the CPU from RUN to STOP and back without removing power. Confirm the same restore behaviour. This isolates the warm restart path; if it fails but the power cycle test passes, the STOP-to-RUN handler is the issue.
5. Cold restart test: Perform a memory reset (MRES) on the CPU, reload the project, and confirm LastCount starts at 0 (because LastCountValid is also reset). The HSC should display 0 on the first scan, not the pre-reset value.
6. Diagnostic buffer check: Open Online > Diagnostics > Diagnostic buffer and look for HSC events (configuration change, error, gate state change) during the test cycles. Filter by "HSC" to reduce noise.
7. Retain budget verification: Open the CPU properties, navigate to "Retentive memory", and verify total usage is well below the CPU limit. A CPU 1214C allows 14 kB; the HSC backup is 4 bytes, leaving plenty of room.
8. Download behaviour test: With the HSC at a known value, perform an online download of a trivial program change and observe whether the retained count is preserved (CPU prompt "Preserve retentive data" must be confirmed). If the count resets, the retain attribute is missing or the download replaced the retain memory image.

12. Cross-Platform Comparison: ControlLogix 1756 HSC

Engineers porting S7-1200 designs to ControlLogix (or maintaining both) will note the conceptual difference. The Allen-Bradley 1756 HSC module, per Rockwell Automation publication 1756-UM007, retains the Stored Value internally across power cycles. The module's "Store and Reset" and "Start" commands write the present value to a non-volatile tag, and the stored value is preserved "until it is overwritten by new data from the next leading edge of a pulse on Input Z."

This means the 1756 module implements the retain pattern at the module level; the CPU program does not need a backup DB. The S7-1200 architecture leaves the retain responsibility to the user program because the HSC lives in the CPU firmware and exposes only the I-address mirror. When migrating a retain pattern from Logix to S7-1200, the equivalent is exactly the buffered-DB approach described in section 4.

The trade-off is module-level integration (1756) versus CPU-level integration (S7-1200). For applications that mix platforms or migrate from Logix, the retain pattern is a familiar engineering exercise rather than a hardware feature.

13. Diagnostic Interrupts and STATUS Byte

The CTRL_HSC STATUS output reports HSC state. A non-zero STATUS indicates an error or warning. Common values documented in the TIA Portal help include:

• STATUS = 0: no error.
• STATUS <> 0: error; refer to the TIA Portal online help for the specific code (typically a configuration or wiring fault).

For HSC-related diagnostic interrupts, enable "Hardware interrupt" in the HSC's device configuration and route the interrupt to an OB (OB40 on S7-1200). The interrupt can be triggered on CV = RV, on direction change, on the gate opening or closing, or on the Z pulse of an A/B encoder. Use the interrupt OB to update the shadow DB immediately, rather than waiting for the next OB1 cycle, if the application has tight timing requirements.

14. Troubleshooting Matrix

15. Field-Proven Caveats

• First-scan order matters. If OB1 runs before OB100 has pushed the retained value, the very first cycle will copy 0 into the shadow and wipe the backup. This is a common bug in projects that have not used OB100. The Siemens execution model is OB100, then OB1, then cyclic; verify the project does not override the startup OB or insert an OB with a higher priority that runs first.
• HSC instance DB and shadow DB are different. The instance DB is created when you place the CTRL_HSC block and holds configuration constants. The shadow DB is a separate global DB the user creates for retention. Do not mark the instance DB as retain and expect it to solve the problem; the instance DB does not hold the live count.
• Multi-channel retention. For encoders on HSC1, HSC3, and HSC5, use three distinct DINTs in the same shadow DB. The retain setting is per-tag, not per-DB, so partial retention is possible. A single DINT per channel, plus a DTL timestamp for the last write, is a clean layout.
• Sign of CV. DINT is signed (–2,147,483,648 to 2,147,483,647). A count of half-revolution plus one of an A/B encoder can roll over. The retention pattern preserves the wrapped value; the application logic must handle the wrap if the range matters. For 32-bit unsigned counting, the HSC instruction output is still a DINT, so the upper range above 2,147,483,647 wraps to negative; convert at the application level if the application expects unsigned.
• Download behaviour. On S7-1200, a download that includes a new hardware configuration or new program resets the retain area by default. Use "Download to device" with the option to "Preserve retain data" where available; otherwise accept the reset during commissioning. For S7-1500, "Memory of retain" survives the download.
• Direction signal handling. If DIR is hardware-controlled (e.g., from a digital input), a power outage that flips the direction bit at restart can produce a different count than expected. Document the direction logic in the project comment and consider latching the direction in a retentive flag in OB100.
• Filter group on shared inputs. The S7-1200 applies the input filter at the filter-group level, not per-terminal. If the HSC is wired to terminals I0.0 and I0.1, and I0.2 through I0.7 are in the same filter group, the slower filter for the standard DI applies to the HSC terminals. Place the HSC terminals on a filter group by themselves, or accept the slower filter and reduce the encoder frequency accordingly.
• Signal board HSC limits. HSC channels on the signal board (SB) have lower maximum frequencies than the onboard HSC channels. The exact limit depends on the SB catalog number and the CPU; consult the SB data sheet. If the application requires > 100 kHz, use the onboard HSC channels, not the SB.
• Diagnostic buffer noise. During normal operation, the diagnostic buffer may log HSC gate state changes, especially if the gate is toggled frequently. Filter the diagnostic buffer view to "HSC" and "configuration change" to reduce noise; the diagnostic buffer is a ring buffer and old entries are overwritten.

16. Commissioning Checklist

1. Wire encoder to the HSC terminals per the CPU data sheet. Verify supply voltage and ground reference.
2. Configure HSC in device configuration: enable, mode, I address, filter, gate, initial value.
3. Create HSC_Retain global DB with LastCount, LastCountValid, FirstRunDone, BootTime, all marked Retain.
4. Insert CTRL_HSC in OB1; wire HW_ID. Verify online that CV tracks the encoder.
5. Add shadow write network in OB1: HSC_Retain.LastCount := CTRL_HSC.CV.
6. Add load network in OB100: write LastCount to CV, pulse NewCV via HSC_LoadPending one-shot.
7. Compile, download to PLC. Accept any retain reset on first download.
8. Run the eight verification steps from section 11. Document the result for the maintenance log.
9. If the CPU is in a high-vibration or high-EMI environment, add input debounce or shielded cable to the encoder wiring; the HSC will not filter electrical noise that the encoder injects into the input.
10. Archive the project and the verification log to the machine documentation folder. Future modifications that re-download the program will reset retain unless the operator confirms "Preserve retentive data".

17. FAQ