S7-1200 1215C: Resolving Sixth SM 1223 DI/DQ Module Fault

Problem Summary

An S7-1200 1215C rack populated with six SM 1223 DI16/DQ16 relay modules, one SM 1231 AI8 thermocouple module, and one SM 1231 AI8 module (eight signal modules total) refuses to complete startup cleanly. The rack sits exactly at the eight-SM ceiling for a CPU 1215C, but the diagnostic buffer accumulates two recurring entries each time the sixth SM 1223 is added: "Fault in lower level component" (an OB82 I/O fault type) and "IO process image fault" (a process image update failure). Five SM 1223 modules plus the two analog SMs comes up cleanly; six SM 1223 modules does not. Slot swapping, cable swapping, and reseating have already been ruled out as root causes.

Hardware Reference - Rack Articles and I/O Map

The rack involved in this scenario is built from current-product S7-1200 signal modules. The following articles and footprints are authoritative; older revision letters (e.g., -0XB0, -0XA8) carry different firmware and should be cross-checked against the TIA Portal device catalog.

Per-slot aggregate for the six SM 1223s alone is 96 DI / 96 DQ plus two AI SMs at 16 AI = 208 external I/O addresses. The CPU 1215C with the V4.x firmware generation scales well above this in raw I/O terms, so the failure is not an address-map ceiling.

Module Count vs S7-1200 Architectural Limits

The S7-1200 SM ceiling is a function of the CPU variant, not of the rack width. The relevant limits for the 1215C are:

The 1215C therefore accepts the eight SMs in question. The failure trigger is not "too many SMs," it is what happens at the sixth SM 1223 specifically. Two boundaries are commonly reached in similar eight-SM racks:

1. 5 V backplane current total for SMs approaches the CPU's 1600 mA supply budget (six SM 1223 at ~180 mA + two SM 1231 at ~80 mA = approx. 1240 mA; leaves ~360 mA of headroom - large enough to not be the limiter, so the trigger is elsewhere).
2. Process image partition (PIP) coverage stops accommodating the configured I/O once the I/O byte count exceeds the PIP0 default partition size and the I/O is not assigned to a custom PIP. The runtime then fails to refresh the overflow bits and logs the IO process image fault at every scan cycle.

Symptoms Decoded - Diagnostic Buffer Entries

The two error texts reported in the S7-1200 diagnostic buffer map to two specific fault categories:

Additional symptoms to look for during inspection:

• SF (system fault) LED illuminated on the CPU and/or SM 1223s.
• BF (bus fault) LED on the CPU flashing while in the failing configuration.
• MAINT (maintenance) LED flashing on the most recently inserted SM 1223.
• Outputs of the sixth SM 1223 stuck at zero or in their pre-update state.
• Analog SMs (AI8, AI8 TC) reading correct data even when digital SM 1223s are faulting - confirming that the analog subsystem is not the trigger.

Root Cause Analysis - The Most Common Triggers

In S7-1200 eight-module racks with mixed digital and analog SMs, six reasons dominate. They should be ruled out in the order listed because each requires a different fix and a different tool. Five of them produce the exact symptom pair this user is seeing.

1. Firmware version mismatch between project and physical SM 1223: the most common trigger. TIA Portal loads the project configuration including the SM firmware version (e.g., V4.4 or V4.6). At project startup, the CPU compares its SM catalog entries to the firmware actually loaded on each SM. Mismatch with the most recent module - here, the sixth SM 1223 - raises OB82 with a "lower level component" message. Slot-swapping does not clear this because the firmware mismatch is on the module, not the slot.
2. CPU startup parameter set to "Compare preset to actual": if the startup setting under CPU Properties > Startup requires exact topology match, a stale configuration download - or one SM module that came from a different revision - trips OB82 on first scan. Set "Startup" to "Warm restart - startup with actual configuration when setpoint configuration does not match" or "No comparison" to bypass.
3. OB82 (or other diagnostic OBs) not loaded in the user program: if OB82 is missing and an I/O fault is raised, the CPU goes to STOP. Once OB82 is present, every SM OB82 entry becomes a recoverable event - but the symptom (lower level component) will keep logging until the underlying mismatch is fixed.
4. Process image partition assignment under-sized: PIP0 default size is small. If the rack contains more I/O bytes than PIP0 covers, the project must assign the overflow bytes to PIP1, PIP2, PIP3, or a custom PIP, and configure OB6x (OB40/OB41/OB42/...) or OB1 to refresh that PIP. Otherwise process image bits beyond PIP0 are stale and the diagnostic buffer logs process image fault once the runtime evaluates them.
5. 24 V supply droop at the last SM terminator: a long 24 V daisy chain or undersized gauge can droop >5% at the rightmost terminator, causing the last SM to brown-out at backplane-power-on. Symptoms overlap with the module-count boundary since the last SM is the most sensitive. Measure at the SM's L+ and M terminals under load.
6. Dust, gold-finish wear, or incorrectly latched T-bus connector: on the sixth SM-to-T-bus interface. This is rare with slot-swap but warrants a re-seat after a firmware update.

Diagnostic Procedure - Online View, Buffer, Firmware Read

Use this ordered procedure to convert an "it won't accept six SM 1223s" statement into a fixable constraint before changing hardware.

1. Open TIA Portal and go online with the CPU. Project tree > expand the PLC > double-click "Devices & Networks" to open the device view. Confirm the connection icon turns green.
2. Verify each SM's identification. Right-click the CPU in the device view > "Online & Diagnostics" > "Online & Diagnostics" tab > "Accessible devices in the target subnet". Browse each slot's actual catalog number and firmware version. Compare with what the TIA Portal offline configuration shows for that slot.
3. Read the diagnostic buffer for the failing configuration. Online > "Online & Diagnostics" > "Diagnostics buffer" tab. Note the timestamp of each "Fault in lower level component" and "IO process image fault". Export or screenshot each entry, because the Event ID and Module/Channel columns identify the slot raising the event.
4. Check OB82 deployment. Project tree > PLC > "Program blocks" > confirm OB82 is present. If absent, the CPU will STOP on the first OB82 trigger when the SM raises a diagnostic interrupt.
5. Check Process Image partitions. In the SM properties, check > "I/O addresses" tab > "Process image partition assignment". Confirm each byte is assigned to a valid PIP (PIP0, PIP1, PIP2, PIP3, custom), or set to "Automatic update (PIP0)" for non-time-critical I/O.
6. Measure the 24 V supply at each SM terminator. With the rack powered and all SMs energized, place a meter on L+/M of the last SM 1223. Voltage should be 20.4-28.8 V DC (CPU 1215C acceptable input range), with ripple <5% under full relay load. Any reading below 20.4 V DC points to a daisy-chain droop.
7. Verify CPU firmware generation. Online & Diagnostics > "Diagnostics" tab on the CPU > "Diagnostics status". The firmware version reported by the CPU must match what the offline project was compiled against.

Firmware Alignment Procedure

If Steps 1-7 of the diagnostic procedure above isolate a firmware version difference between TIA Portal and the installed SMs, perform the following in order. The procedural source for installing and removing S7-1200 modules is the official Siemens module installation guide (Siemens S7-1200 module installation guide) - this URL anchors every mechanical step below.

1. Bring the project's offline configuration to match the desired firmware. In Device View, select each SM and open Properties > "Catalog" - pick the catalog SM whose revision letter matches the physical module and the firmware version TIA Portal offers. Recompile the hardware configuration and download to the CPU.
2. Update SM firmware via online access. Online & Diagnostics > select the SM at slot 6 (or whichever slot is faulting) > "Firmware update" > select the .upd file matching the desired firmware version (e.g., V4.6.0). Click "Run update" and wait for the SM's LED pattern to return to RUN/green. The SM will reset during the update.
3. Update CPU firmware if the project was compiled against a newer CPU firmware. Online & Diagnostics > select the CPU > "Firmware update" tab > choose the .upd file. The CPU accepts the firmware update only if no active password is required and the SM modules are powered.
4. Adjust the CPU startup parameter to "Warm restart - startup with actual configuration when setpoint configuration does not match": this relaxes the strict topology check and tolerates minor catalog revisions downstream. Save and recompile.
5. Recompile and re-download the entire hardware configuration. "Project tree > PLC > Compile > Hardware (rebuild all)". Then download to the CPU.
6. Clear the diagnostic buffer and power cycle the rack. Confirm the previously failing configuration no longer raises the two events after a 30-second warmup.

Hardware Installation Verification

Even with firmware aligned, mechanical issues can resurrect the same symptom. The official Siemens module installation guide covers the T-bus connector and side-lock-tab engagement, and must be verified in this exact order for every SM 1223 in the rack.

1. Power off and lock out the rack. Remove the 24 V DC supply cable from the CPU's L+/M terminals.
2. Remove the SM terminator on the right-hand side of the rack. Slide each SM upward off the DIN rail by releasing the side-locking tabs, then pull the module away from the T-bus connector. Refer to the Siemens S7-1200 module installation guide for the standard removal sequence.
3. Inspect the T-bus connector for contamination. The gold fingers on the rear of each SM must sit on the connector without oil, dust, or debris. Wipe with isopropyl alcohol and a lint-free swab.
4. Re-install in reverse order. The T-bus connector must be slid into the rail groove first. Each SM hooks onto the rail, then rotates downward and clicks into the T-bus. Side-locking tabs are pressed outward after each SM to grip the neighboring module.
5. Reinstall the rightmost terminator. The terminator is mandatory and provides 24 V termination for the rack's internal 5 V rail.
6. Re-apply 24 V DC. Wait for the CPU's STOP/RUN LED to settle before the next step.
7. Verify ONLINE > Accessible devices in TIA Portal shows all eight SMs without an SF or BF flag. If the original fault returns, proceed to process image or power-budget sections.

Process Image and OB1 Update Configuration

SM 1223 DI16/DQ16 modules place 16 DI bits and 16 DQ bits per slot into the process image. Six of them produce 6 * 4 bytes = 24 bytes of digital I/O plus the AI SMs. PIP0 default size comfortably accommodates this for a 1215C, so the trigger is more often the assignment method than the size.

If PIP1-PIP3 OB blocks are listed in the project and triggered by hardware interrupts on selected channels of the first SM 1223, only PIP0 is sized to "automatic," and the remaining SM 1223 I/O must also be assigned a PIP. The right pattern:

1. Open SM 1223 (slot 2) > Properties > I/O addresses > "Process image partition assignment" - set both DI and DQ bytes to "Automatic update (PIP0)" for all SMs that are not wired to a hardware-interrupt channel.
2. For SMs whose channels feed OB40/OB41/OB42, assign those specific I/O bytes to PIP1/PIP2/PIP3 and confirm OB40/OB41/OB42 exist in the project.
3. Recompile and download.

If a custom PIP assignment is used and the OB that refreshes it is missing, the process image fault log entry appears at every OB1 cycle.

5 V Backplane and 24 V Power Budget

The CPU 1215C supplies 1600 mA on the 5 V backplane for SMs and 200 mA for the CPU internal logic, with a typical budget for the rack's slot population as follows:

The 1215C can technically power this load; however, the relay-cycle current on the 24 V rail can fold onto the 5 V regulator when all six SM 1223s simultaneously close contacts. Forcing at heavy relay loads can produce a brief sag. Switch the 24 V rail feeding the rack's field side to a regulated 24 V DC supply rated at the sum of worst-case relay pickup currents (six SM 1223 x 2 A per point x de-rating; in practice, derate each relay common to 5 A continuous despite the 10 A spec).

Slot Order and SM Placement Rules

The S7-1200 module installation guide from Siemens specifies mechanical order. For a fault-resilient eight-SM rack, place modules in this order:

1. Slot 1 - CPU 1215C (must be leftmost).
2. Slots 2-7 - SM 1223 (digital) in the same article group, six instances, identical firmware revisions.
3. Slot 8 - SM 1231 AI8 (voltage/current).
4. If using an SM 1231 AI8 TC, place it last (rightmost terminator side).

Verification and Re-Test Procedure

1. Re-download the compiled hardware configuration to the CPU.
2. Set the CPU to RUN.
3. Observe CPU LEDs - STATE = green solid, SF = off, BF = off, MAINT = green solid if firmware version is current, off if not.
4. Open Online & Diagnostics > Diagnostics buffer. Confirm two entries:

• One "Diagnostic interrupt cleared" at the most recent restart.
• No "Fault in lower level component" or "IO process image fault" entries after the firmware update.

5. Force each DO of every SM 1223 from a watch table and confirm physical relay action. Required to rule out cold-solder joint and verify each module's output path.
6. Force and read each DI of every SM 1223 to confirm input path.
7. Force each AI channel and verify analog value in the watch table.
8. Burn the rack in for 24 hours with a watchdog task that exercises at least one DO on each SM 1223 per minute. Clear the diagnostic buffer afterward and confirm zero new fault entries.

Preventive Best Practices

Once the rack has been corrected, lock down the configuration so the same fault cannot reappear when the next engineer pulls a backup of the project:

• Use a single article number across all six SM 1223s. One revision letter across the rack. Mixing -0XA8 (Firmware V3.x) with -0XB0 (Firmware V4.x) raises the firmware-mismatch surface area significantly.
• Lock the SM firmware in TIA Portal. Device view > SM properties > "Firmware" - choose "Use latest" vs "Use selected" and select the desired version. Compile and document this decision so future compiles stay anchored.
• Deploy the firmware set via SIMATIC Memory Card. With a SIMATIC MC containing the CPU firmware image, you can roll forward or back without a TIA Portal host connection to the rack.
• Always load OB82, OB83, OB100, OB101, OB102. A complete diagnostic OB set lets the CPU log OB82 I/O faults as recoverable. Missing OB82 turns the same fault into a CPU STOP.
• Configure PIP0 automatic for non-time-critical I/O. Assign hardware-interrupt channels to PIP1-PIP3 only when needed. This keeps the diagnostic buffer quiet and avoids the I/O process image fault trap.
• Document module sequence in TIA Portal "Project tree > Documentation > Export." Attach the export to the as-built drawing, so the next engineer can verify slots quickly.
• Use the SIMATIC Automation Tool for fleet updates. Multi-machine builds with the same rack layout can be brought forward to a single firmware level with one push, which keeps inter-rack diagnostics consistent.

FAQ