S7-1200 Analog Output Rate Limiter Using TIA Portal V13 Cyclic OB

Field-tested procedure for ramping a SIMATIC S7-1200 analog output toward a commanded setpoint at a fixed rate (200 raw units per second), with working SCL and LAD code in TIA Portal V13 SP1 / STEP 7 Basic V13 SP1. The pattern is generic and applies to any CPU 1211C/1212C/1214C/1215C/1217C.

1. Problem Statement and Requirements

An operator enters a percentage between 0 and 100 on an HMI tag. The PLC must convert that percentage to a raw analog value in the Siemens integer range 0–27648 (the canonical range for 0–10 V or 0/4–20 mA on the onboard analog outputs of the CPU 1214C and on SM analog output modules).

If the operator jumps from 0 % to 100 % in a single step, the raw integer is not allowed to step directly to 27648. The process variable must rise in increments of 200 units per second. Likewise, on a decreasing command it must fall by 200 units per second until it reaches the commanded value. The conversion can be summarized as:

The scaling from percentage to raw value uses the standard Siemens linear conversion:

Sp_Raw = (Sp_Pct * 27648) / 100

For a CPU 1214C DC/DC/DC (6ES7214-1AG40-0XB0) the two onboard analog outputs are addressed as %AQ0 and %AQ2 (the two-word alignment is fixed by the analog output channel granularity). For the DC/DC/RLY variant (6ES7214-1BG40-0XB0) you must add an SB 1232 or SM 1232 analog output module – there is no onboard AQ on the relay variant. Refer to the S7-1200 Programmable Controller System Manual, section 6.3 "Analog outputs", for channel address layout.

2. Why CTRL_HSC_EXT Is the Wrong Block

CTRL_HSC_EXT (and its smaller cousin CTRL_HSC) are HSC (High Speed Counter) control blocks from the "Counters and Measurement" technology object family in TIA Portal. They are designed to:

• Configure a hardware counter channel (CU, CD, or incremental encoder).
• Load a comparison value, set a hardware interrupt threshold, and reset the counter.
• Read measured frequency / period / velocity from the HSC hardware.

None of these functions enforce a rate of change on an INT tag. CTRL_HSC_EXT cannot be told "increase this INT by 200 every 1000 ms until it equals Sp_Raw". It operates on a 32-bit counter hardware register, not on user memory, and it does not call a user-defined ramp function. If you wire CTRL_HSC_EXT into the program you will compile successfully but the rate-limit logic will never run.

Discard the HSC path. Use a cyclic interrupt OB instead.

3. Architecture Overview

4. Prerequisites

If TIA Portal V13 SP1 is not yet installed, obtain the package from the Siemens Industry Online Support portal. Newer TIA Portal versions (V15, V16, V17) are backward-compatible with the V13 SP1 project but V13 SP1 cannot open projects saved by V14+.

5. Step 1 — Define the Tags

In the PLC tag table, add the following global tags. Right-click PLC tags → Add new tag table, then create:

6. Step 2 — Create the Function Block "RampLimiter"

The FB encapsulates the rate-limit math so it can be reused if you later add a second analog channel with a different slew rate. In the project tree, add Program blocks → Add new block → Function Block, name it RampLimiter, language SCL.

6.1 SCL Implementation

FUNCTION_BLOCK "RampLimiter"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 0.1
   VAR_INPUT
      Sp_Raw       : INT;     // commanded value 0..27648
      StepRate     : INT;     // units per OB cycle (default 200)
      Enable       : BOOL;    // 1 = ramp, 0 = hold
   END_VAR
   VAR_OUTPUT
      Out_Raw      : INT;     // ramped value
      Done         : BOOL;    // 1 when reached setpoint
      Error        : WORD;    // 0 = OK, 16#0001 = invalid range
   END_VAR
   VAR
      Diff         : DINT;    // signed difference
   END_VAR
   VAR RETAIN
      Out_Raw_R    : INT;     // internal retained copy
   END_VAR
BEGIN
   Error := 16#0000;
   Done := FALSE;

   // ---- 1. Range guard ----
   IF (Sp_Raw < 0) OR (Sp_Raw > 27648) OR (StepRate <= 0) THEN
       Error := 16#0001;
       Out_Raw := Out_Raw_R;
       RETURN;
   END_IF;

   // ---- 2. Initialise retained memory on first call ----
   IF NOT Enable THEN
       Out_Raw := Out_Raw_R;
       RETURN;
   END_IF;

   // ---- 3. Compute signed difference ----
   Diff := INT_TO_DINT(Sp_Raw) - INT_TO_DINT(Out_Raw_R);

   // ---- 4. Apply rate-limited step ----
   IF ABS(Diff) <= INT_TO_DINT(StepRate) THEN
       // Within one step of target — snap to setpoint
       Out_Raw_R := Sp_Raw;
       Done := TRUE;
   ELSIF Diff > 0 THEN
       // Ramping up
       Out_Raw_R := Out_Raw_R + StepRate;
   ELSE
       // Ramping down, guard against INT underflow
       Out_Raw_R := Out_Raw_R - StepRate;
   END_IF;

   // ---- 5. Saturate ----
   IF Out_Raw_R < 0 THEN Out_Raw_R := 0; END_IF;
   IF Out_Raw_R > 27648 THEN Out_Raw_R := 27648; END_IF;

   Out_Raw := Out_Raw_R;
END_FUNCTION_BLOCK

Key engineering points:

• INT + INT can overflow. Two INT values up to 27648 cannot exceed 32767 (max INT), so Out_Raw_R + StepRate is safe. If you later raise the maximum to 32767 or higher you must convert to DINT before addition.
• The "snap-to-target" branch prevents the output from oscillating forever around the setpoint when the residual error is smaller than one step.
• Retain on Out_Raw_R preserves the ramp position through a CPU restart. If you do not want that behaviour, remove RETAIN and the output will reset to 0 on every restart.

6.2 LAD Equivalent (for Engineers Who Prefer Ladder)

If SCL is not available or your site standard mandates LAD, the equivalent is a network of compares, additions, and a SET/RESET flip-flop. The structure is identical; here is a network-by-network summary.

// Network 1 — range guard
A    Sp_Raw
L    0
<I
S    Error_Flag         // on if negative
A    Sp_Raw
L    27648
>I
S    Error_Flag         // on if above max
A    Error_Flag
BEC                     // skip remainder if invalid

// Network 2 — load retained Out_Raw_R into working word
L    Out_Raw_R
T    Out_Raw

// Network 3 — done / next-step direction
L    Sp_Raw
L    Out_Raw_R
-I
T    Diff
L    0
>I
=    RampUp             // Diff > 0 → must go up
L    Diff
ABS
L    StepRate
>=I
=    WithinOneStep

// Network 4 — apply step
A    WithinOneStep
JCN  NO1
L    Sp_Raw
T    Out_Raw_R
S    Done
JU  END_STEP
NO1: A  RampUp
JCN  NO2
L    Out_Raw_R
L    StepRate
+I
T    Out_Raw_R
JU  END_STEP
NO2: L  Out_Raw_R
L    StepRate
-I
T    Out_Raw_R
END_STEP: NOP 0

// Network 5 — saturate at 0 and 27648
L    Out_Raw_R
L    0
<I
JCN  SAT1
L    0
T    Out_Raw_R
SAT1: L    Out_Raw_R
L    27648
>I
JCN  SAT2
L    27648
T    Out_Raw_R
SAT2: L    Out_Raw_R
T    Out_Raw

For a visual representation, the I/O is identical to the SCL version. Network 4 implements the up/down/snap branches with conditional jumps.

7. Step 3 — Create the Cyclic Interrupt OB30

Add Program blocks → Add new block → Organization Block → OB type: Cyclic interrupt. Name it Main_Ramp_Cyclic. After creation, open its properties and set the Cycle time to 1000 ms and the Phase offset to 0 ms (or any value that does not collide with other cyclic OBs).

Inside OB30, call the FB once per firing:

// Main_Ramp_Cyclic — fires every 1000 ms
IF TRUE THEN
    "Ramp_DB"(   // instance DB for RampLimiter
        Sp_Raw   := "Sp_Raw",
        StepRate := "StepRate",
        Enable   := TRUE,
        Out_Raw  => "Out_Raw",
        Done     => "Done_Tag",
        Error    => "Err_Tag"
    );

    // Hand ramped value to physical analog output
    %AQ0 := "Out_Raw";
END_IF;

OB30 runs independently of the main scan. Even if OB1 spends 50 ms on a heavy block, OB30 still fires on the configured 1000 ms grid because the cyclic interrupt is dispatched by the S7-1200 firmware scheduler before the next user cycle finishes.

8. Step 4 — Scaling in OB1

OB1 only needs to convert Sp_Pct (0–100) to Sp_Raw (0–27648). Keep this in the main cycle because the operator HMI tag changes asynchronously and 1 ms latency is fine.

// OB1 Segment 1 — percent to raw conversion
"Sp_Raw" := ("Sp_Pct" * 27648) / 100;

If you prefer floating-point and round-trips through REAL, the equivalent is:

// REAL scaling variant
#sp_real := INT_TO_REAL("Sp_Pct") / 100.0;
"Sp_Raw" := REAL_TO_INT(#sp_real * 27648.0);

For the integer variant, watch the rounding direction. Siemens rounds toward zero. For an operator entry of "100" the result is exactly 27648. For "1" the result is 276. For "37" the result is 10229. If your process cannot tolerate this quantisation, use the REAL path and round explicitly with ROUND or CEIL before REAL_TO_INT.

9. Step 5 — Configure the Analog Output

In Devices & Networks, double-click the analog output channel of the CPU 1214C (or SM 1232). Set:

The CPU writes the integer 0 to 27648 into the analog channel and the firmware converts it to the physical voltage or current. See the S7-1200 System Manual, section "Representation of analog values".

10. Verification and Commissioning

1. Download the project to the CPU 1214C and place the CPU in RUN.
2. Watch table test: open PLC → Watch & force tables → Add watch table. Add Sp_Pct, Sp_Raw, Out_Raw, %AQ0, Done_Tag.
3. Force Sp_Pct = 0 and let Out_Raw settle at 0. Confirm %AQ0 reads 0.
4. Force Sp_Pct = 100. Out_Raw should rise by exactly 200 each second: 0, 200, 400, 600, ... up to 27648. The transition takes 138.24 seconds. Confirm monotonic increase in the watch table (force periodic refresh <= 1 s).
5. Force Sp_Pct = 50 mid-ramp. Out_Raw should reverse direction within one OB30 cycle, falling at 200 units/s until it hits 13824 (50 % of 27648).
6. Force Sp_Pct = 49 (within one step of current value if currently at 13824). Done_Tag should turn on at the next OB30 firing because the snap-to-target branch fires.
7. Disconnect the field loop (4–20 mA only). The wire-break diagnostic should trigger an I/O fault. OB30 keeps running and updating Out_Raw, but %AQ0 will not physically drive the field if hardware output is disabled. Always re-evaluate the safety implication of this behaviour in your risk assessment.
8. STOP→RUN test: cycle the CPU mode. If Out_Raw_R is RETAIN it resumes at its last value; otherwise it resets to 0 and climbs again.

11. Edge Cases and Field Caveats

11.1 Faster Cycle Time

If you need a finer ramp granularity, drop OB30 cycle to 100 ms and scale StepRate to 20 (still 200 units/s). The S7-1200 minimum cycle time for OB30 is 1 ms, but anything below 5 ms is unsafe in cyclic interrupt OB 30 — use OB35–OB38 (configured 1 ms minimum) if you need sub-millisecond timing. The arithmetic remains identical.

11.2 Multi-Channel

If you need two channels ramping independently, declare two instance DBs ("Ramp_DB_Ch0", "Ramp_DB_Ch1") and call the FB twice inside OB30. The CPU 1214C DC/DC/DC has two onboard outputs (%AQ0 and %AQ2). Add a separate StepRate tag per channel if rates differ.

11.3 HMI Smoothing

If the operator knob on the HMI is also being polled, the HMI may not see a smooth ramp because it reads Sp_Pct (the command), not Out_Raw. Bind the HMI display to Out_Raw via a separate tag (Sp_Display). Otherwise the operator will see the command jump to 100 even though the field value is still ramping up.

11.4 Network Dropout / HMI Disconnect

If the HMI connection fails, Sp_Pct retains its last value because it lives in the PLC tag table. Out_Raw continues to ramp toward the last command. This is the desired behaviour for most processes — a stuck ramp at the last command is safer than a snap to zero — but document the behaviour in your FMEA.

11.5 Saturation Math

If Sp_Raw suddenly flips from 27648 to 0 the ramp falls 200 per second. At that rate it takes 138.24 s to reach 0. Some processes (e.g. pneumatic valves) require a different down-rate than up-rate. Add a StepRate_Dn input to the FB and select inside the down-branch:

// Replace the down-step in the FB with:
ELSIF Diff < 0 THEN
    IF StepRate_Dn > 0 THEN
        Out_Raw_R := Out_Raw_R - StepRate_Dn;
    ELSE
        Out_Raw_R := Out_Raw_R - StepRate;
    END_IF;
END_IF;

11.6 Skip OB30 on a Slow Scan

If the user program overruns and the cyclic OB misses its scheduled phase, the S7-1200 firmware generates an OB80 (time error) and either calls the OB80 error handler or logs a diagnostic entry. By default the CPU stays in RUN and the late OB30 fires immediately. If your application depends on a precise ramp time you must enable OB80 and count skipped firings.

12. Common Errors and Error Matrix

13. Alternate Implementations

13.1 IEC 61131-3 Standard Timer Block (No Cyclic OB)

If your plant standard disallows cyclic OBs, you can implement the ramp in OB1 using a TP (pulse timer) at 1000 ms triggering a single increment. This works but ties the ramp to the main scan, which can drift under heavy CPU load. Use it only if the rate precision is non-critical.

13.2 S7-1500 Equivalent

On S7-1500 the same logic applies, but use the Runtime OB (OB30) under the new naming convention and enable optimisations in the FB. The IEC timer resolution is higher and you can drop StepRate to 1 with a 10 ms OB30 to get smoother ramps. See the SIMATIC S7-1500 Automation System Manual.

13.3 Using the PLC Web Server

On CPU 1214C firmware V4.0 and above with the Web Server activated, you can read Out_Raw in a browser at http://<plc-ip>/. Useful for sanity checks during commissioning when the HMI is not yet connected.

14. Performance and Resource Budget

The ramp adds essentially no scan-time load and consumes less than 1 % of the 1214C's user memory budget.

15. Putting It Together — The Full Control Loop

Once the ramp block is in place, the entire process loop is:

1. Operator entry — HMI tag Sp_Pct (0–100).
2. Scale — OB1 converts Sp_Pct to Sp_Raw (0–27648) using integer math.
3. Ramp — OB30 fires every 1000 ms; FB "RampLimiter" walks Out_Raw toward Sp_Raw at 200 units/s, with saturation and snap-to-target.
4. Output — OB30 writes Out_Raw to %AQ0; the onboard analog converts it to 0–10 V or 4–20 mA.
5. Feedback (optional) — An analog input monitors the field; compare to Out_Raw to detect stuck actuator. This is outside the ramp logic but is the natural place to add process safety.

For further background on Siemens analog value representation and the S7-1200 cyclic interrupt model, refer to the SIMATIC S7-1200 Programmable Controller System Manual, the STEP 7 Basic V13 SP1 Programming and Operating Manual, and Siemens application entry "Cyclic interrupt OBs" in the Industry Online Support knowledge base.