S7-1200 CPU Selection Guide: Sizing 1211 to 1217 Models

Selecting the correct SIMATIC S7-1200 CPU is the first engineering decision in any small control-cabinet project and directly affects the cost of the bill of materials, panel layout, I/O expansion budget, and the long-term serviceability of the program. This guide walks through the on-board I/O, work memory, special-function channels (high-speed counters, PTO, PWM), PID capacity, and communication ports of every CPU 1211C, CPU 1212C, CPU 1214C, CPU 1215C, and CPU 1217C, then shows a deterministic sizing workflow that you can apply during cost estimating without owning the hardware yet. All values are pulled from the SIMATIC S7-1200 Programmable Controller System Manual and cross-referenced with the SIMATIC TIA Selection Tool. Verify the final figures against the manual revision current at the time of quotation, because firmware 4.x expanded PTO, OPC UA, and trace capabilities on the smaller CPUs.

1. S7-1200 CPU Family at a Glance

The S7-1200 family is a single-line scalable controller that uses the same STEP 7 (TIA Portal) programming environment, the same signal modules (SM), the same communication modules (CM/CP), and the same board-level add-ons (SB, BB) across all five CPU variants. The differences between the five models are concentrated in five dimensions:

1. On-board digital and analog I/O count (cannot be reduced, only expanded with SM/SB).
2. Work memory (data) and load memory (code) available to the user program.
3. High-speed counter (HSC), pulse-train output (PTO), and pulse-width modulation (PWM) channel count.
4. Number of PID_Compact / PID_3Step / PID_Temp instances the firmware can run in parallel without scan-time penalty.
5. Communication ports — PROFINET port count, PROFIBUS master/slave capability, RS-232/RS-485 point-to-point protocols, OPC UA, and Modbus TCP server capacity.

If you know the dimensions above for your application, the CPU choice is a one-line decision. If you do not know them, the rest of this guide builds them in the right order.

2. On-Board I/O Comparison Table

The on-board I/O cannot be removed. Every digital input on a 1211C is also a high-speed counter or interrupt input candidate. Every digital output on a 1217C supports 24 V at 0.5 A and can be configured as PWM or PTO. The table below is the canonical reference. Check the S7-1200 system manual for the exact wiring diagram (sink/source, PNP/NPN) and the 24 V sensor supply current budget.

3. Work Memory, Load Memory, and Retentive Memory

Program capacity is the second gating constraint. S7-1200 separates three memory areas:

• Load memory — non-volatile; holds the compiled project (code + data) in the SIMATIC Memory Card or internal flash. Recovered on power loss.
• Work memory — volatile; the runtime RAM the CPU uses to execute the code and hold the current values of DBs. Lost on power loss unless backed by retain attributes.
• Retentive memory — a reserved slice of work memory that survives power loss, configured per tag, M-bit, or instance-DB.

The exact split between code and data work memory is firmware-dependent. On firmware 4.x the split is roughly 50/50 (e.g., 1217C: 75 KB code + 75 KB data), but the user-facing total is what you should size against. Field experience: a 1214C at firmware 2.2 will run out of work memory on a moderately complex machine (recipe DBs, several FB instances, motion blocks). The same program fits comfortably on a 1215C at firmware 3.0 because the work memory roughly doubled and the compiler is more efficient.

Sizing heuristic: Before you commit, build the program against the smallest CPU in the candidate list, then check the resource utilization in TIA Portal. If a single resource approaches 85–90 %, step up one model. If the resource still trends upward as features are added, jump two.

4. Special-Function Channels: HSC, PTO, PWM

The high-speed counter, PTO, and PWM channels live on the digital inputs/outputs of the CPU itself and on the front-pluggable Signal Board (SB). They are not on the SMs. This is the single most overlooked source of CPU mis-selection.

On the CPU 1215C and 1217C, outputs Q0.0 and Q0.1 support 1 MHz PTO with differential signalling through the SB 1222 DQ 4 × 24 V / 200 kHz (order code 6ES7222-1AD30-0XB0) or 1 MHz differential SB. If a servo drive expects 5 V differential step/dir, add the SB 1222 DQ 4 × 5 V / 200 kHz (6ES7222-1AD50-0XB0 family). The 1211C/1212C/1214C top out at 100 kHz on-board.

5. PID Control Capacity

All S7-1200 CPUs run the PID_Compact, PID_3Step, and (firmware 4.0+) PID_Temp instruction blocks. The hard limit is the OB1 scan time and the work memory footprint of each loop:

• Each PID_Compact instance consumes roughly 1.5–2.5 KB of work memory plus its background DB.
• The cycle time of the PID block should be ≥ 10 ms. On a 1211C running 8 loops with a 20 ms PID sample time, the residual OB1 bandwidth collapses to single-digit milliseconds, which makes HSC and PTO jitter visible.
• Siemens documentation in the PID commissioning manual recommends the 1215C/1217C class when more than 6–8 loops are running concurrently with high-speed motion on the same scan.

Practical ceiling observed in field deployments:

6. Communication Interfaces

The 1215C and 1217C have two PROFINET ports on the bottom, internally switched. This lets you split the machine network (PROFINET to drives) from the plant network (PROFINET to HMI / SCADA) without an external managed switch, which is often the deciding factor on a cost estimate.

All CPUs accept the same communication modules:

• CM 1241 RS-232 (6ES7241-1AH32-0XB0) — point-to-point ASCII, Modbus RTU master/slave, USS.
• CM 1241 RS-422/485 (6ES7241-1CH32-0XB0) — same protocols, half-duplex RS-485 two-wire for multi-drop Modbus.
• CB 1241 RS-485 (6ES7241-1CH30-1XB0) — board-level, 1 slot only.
• CM 1242-5 (PROFIBUS DP slave) and CM 1243-5 (PROFIBUS DP master) for legacy fieldbus.
• CP 1243-1 (industrial security / firewall for cloud and remote access).

7. Cycle Time and Bit-Operation Performance

S7-1200 cycle time scales with the program and the I/O update, but the underlying bit-operation throughput is the same hardware IP core across the family. The differentiation is in I/O throughput, communication tasks, and PID/motion blocks running in parallel.

Approximate instruction execution times (firmware 4.x, from the S7-1200 system manual):

Use these to estimate OB1 load:

OB1_Time_ms ≈ (0.0002 × N_bit + 0.0023 × N_word + 0.0025 × N_real + 0.009 × N_math) + 0.2_ms_IO_update + 0.5_ms_comm

If the resulting OB1 time is above 50 ms on a 1211C/1212C, the HSC, PTO, and PID tuning will start to oscillate. The 1215C and 1217C do not run the bit/word core faster, but they have more memory and a more efficient compiler, so the same program ends up with fewer instructions and a tighter cycle.

8. Power Supply and Wiring Variants

Each CPU ships in three power variants that affect the MLFB and the wiring design but not the I/O count or memory:

• DC/DC/DC — 24 V DC power supply, 24 V DC digital inputs, 24 V DC transistor outputs (0.5 A per output, 1.0 A peak).
• DC/DC/RLY — 24 V DC power, 24 V DC inputs, relay outputs (2 A per point, 10 A per common).
• AC/DC/RLY — 85–264 V AC power, 24 V DC inputs, relay outputs. Available on 1211C/1212C/1214C only; not offered on 1215C and 1217C because the cabinet typically already has 24 V DC from a SITOP.

For control-box design, the DC/DC/DC variant is preferred when driving solid-state relays, frequency inverters, or stepper drives directly. The DC/DC/RLY variant is preferred for valve banks, motor contactors, and any load above 0.5 A or below 24 V.

9. CPU Selection Methodology (Step-by-Step)

Use this workflow during cost estimating or at the start of a project. It is intentionally conservative so that the BOM does not have to be re-cut halfway through FAT.

Step 1 — Build the I/O list

Enumerate every digital input, digital output, analog input, analog output, high-speed counter, PTO, PWM, and serial port. Add a column for on-board vs. SM/SB. Use the SIMATIC TIA Selection Tool to validate the topology. Tool: SIMATIC TIA Selection Tool.

Step 2 — Apply the I/O contingency margin

Increase the totals based on project risk:

• Stable, high-volume product (1000+ units, fully spec'd): add 0–5 % spare I/O.
• Standard, mid-volume (50–500 units): add 20 % spare I/O.
• One-off, prototype, or early-stage development: add 40 % spare I/O.

If the inflated count exceeds the on-board I/O of the target CPU, escalate one model up — or specify an SM to absorb the difference.

Step 3 — Decide special-function channels

Pull the worst-case HSC, PTO, and PWM requirements from the machine specification. Map them to the channel table in Section 4. If a 1 MHz PTO is required, the 1211C/1212C/1214C are disqualified on hardware and the 1215C/1217C becomes the floor.

Step 4 — Estimate PID and motion load

Count the closed-loop controllers, the axes, and the sample times. If total motion + PID exceeds the comfort ceiling in Section 5, escalate. The cost of stepping from 1214C to 1215C is small compared with the cost of a re-spin during commissioning.

Step 5 — Compile against the smallest candidate

Write the code on the smallest CPU in the candidate list and let TIA Portal report work memory, retentive memory, and the bit/word/real mix. Step the CPU up one model if any resource trends past 85 %. Step two models if it trends past 90 % during the first build.

Step 6 — Lock the BOM

Choose the lowest CPU that passes all five steps. The only exception is standardization: if the project house runs 95 % of its machines on a 1215C, the cost of the spare-parts inventory and the engineering ramp-up on a 1214C may justify a non-minimum BOM.

10. Sample Selection Walkthroughs

Walkthrough A — Small filling machine, 12 DI / 8 DO / 2 AI, no motion, 2 PID loops

1. I/O list: 12 DI / 8 DO / 2 AI = 22 points. After 20 % margin: 27 points. The on-board 14 DI / 10 DO / 2 AI of the 1214C absorbs it directly with no SM.
2. Special functions: none.
3. PID: 2 loops. All CPUs handle it.
4. Memory: scan-based program, no recipes. 25 KB is sufficient.
5. Selection: CPU 1212C DC/DC/RLY if the 8 DO can be relay; 1214C otherwise for headroom. The 1211C is disqualified because it has no SM slot and 12 DI is too close to the 6-DI ceiling.

Walkthrough B — Servo-driven pick-and-place, 8 DI / 6 DO, 1 PTO 200 kHz, 2 HSC, 1 PID

1. I/O list: 14 points. The 1212C (8/6/2) handles on-board with one SM or SB.
2. Special functions: 1 PTO 200 kHz. The 1212C supports 100 kHz on-board → SB 1222 200 kHz required, or escalate to 1215C for 1 MHz on-board.
3. PID: 1 loop. All CPUs handle it.
4. Selection: CPU 1215C DC/DC/DC is the cleanest fit. The 1212C is workable but the SB 200 kHz limits the encoder feedback on the same scan.

Walkthrough C — HVAC control panel, 20 DI / 14 DO / 4 AI / 2 AO, 6 PID loops, Modbus RTU to legacy chiller

1. I/O list: 40 points. After 20 % margin: 48 points. The 1215C on-board (14/10/2/2) plus one SM 1231 AI 8 and one SM 1223 DI 16/DO 16 → 48 points handled.
2. Special functions: none.
3. PID: 6 loops — 1214C is workable, 1215C is comfortable.
4. Modbus RTU: CM 1241 RS-422/485.
5. Selection: CPU 1215C DC/DC/RLY with one CM 1241 and two SMs.

11. Standardization vs. Minimum-Fit Strategy

Two valid procurement strategies exist:

• Minimum-fit: Pick the smallest CPU that satisfies the I/O, memory, and special-function table. Lowest unit cost, smallest panel footprint, lowest battery/SD-card cost. Risk: if the customer adds features late, an in-field swap to a larger CPU costs more than the savings on day one.
• Standardize on 1215C: 100 KB work memory, 4 MB load memory, two PROFINET ports, 1 MHz PTO, full OPC UA. Covering 80–90 % of small control-box applications with one MLFB streamlines the spare-parts inventory and the engineering training.

For one-off or low-volume projects the minimum-fit strategy wins on price. For panel shops that build dozens of similar control boxes a year, the 1215C standardization pays back in the second year.

12. Migration Path to S7-1500

If the program trends past 150 KB of work memory, the S7-1500 family becomes the next step. The migration is not automatic; the program must be re-imported and the data types re-validated. Signs that the project has outgrown the S7-1200:

• More than 16 axes of motion.
• More than 32 PID loops with sub-10 ms sample time.
• Need for OPC UA Pub/Sub, MQTT, or full security events.
• Trace recording of 50+ tags for longer than 10 s.
• PROFINET IRT with isochronous mode.

For projects that fit inside the 1217C envelope, the S7-1500 is over-spec'd. The 1217C remains the S7-1200 ceiling and is the most capable controller you can quote in the family.

13. Cost-Side Considerations

The CPU is one of the smaller lines on the control-box invoice. A typical bill of materials for a 30-I/O box contains:

• Enclosure, DIN rail, wire duct, terminals: 35–45 % of material cost.
• Power supply (SITOP or equivalent): 8–12 %.
• Wiring, ferrules, marking: 10–15 %.
• CPU + SM + CM: 20–30 %.
• Engineering hours (programming, FAT): larger than the hardware cost on a one-off.

Stepping the CPU from 1212C to 1215C adds a single-digit percentage to the total project cost, while saving engineering hours and reducing the risk of a CPU swap in the field. This is the economic argument for standardization when the application is close to the boundary.

14. Common Sizing Errors and How to Avoid Them

15. Verification Checklist Before Releasing the BOM

1. ☐ I/O count (including 20–40 % margin) is ≤ CPU on-board + SM capacity.
2. ☐ HSC, PTO, PWM channel count is ≤ CPU hardware limit and matches the firmware revision.
3. ☐ PID loop count is ≤ the comfort ceiling in Section 5.
4. ☐ Communication ports (PROFINET, Modbus, PROFIBUS) match the architecture diagram.
5. ☐ Retentive memory ≥ recipe DB + persistent M-bits.
6. ☐ Power supply variant (DC/DC/DC, DC/DC/RLY, AC/DC/RLY) matches the cabinet supply.
7. ☐ Sensor supply current (typically 400 mA total on-board) is ≥ the sum of all connected sensors.
8. ☐ SD card / SIMATIC Memory Card sized ≥ load memory requirement.
9. ☐ TIA Portal project compiles against the selected CPU, no implicit data-type widening warnings.
10. ☐ Resource utilization in TIA Portal < 85 % on every category.

16. Reference Documents and Tools

• Siemens Industry Online Support — entry point for manuals, firmware updates, and application examples. Search for "S7-1200 system manual" to pull the latest revision (manual entry 109741593 family, in the S7-1200 category).
• SIMATIC TIA Selection Tool — drag-and-drop configurator for the S7-1200 station. Validates I/O count, slot order, and power budget. Generates a BOM with valid MLFBs.
• S7-1200 Programmable Controller System Manual — the canonical reference for memory limits, I/O electrical specs, HSC wiring, and PTO/PWM configuration. Verify every spec in this manual before locking the BOM; do not rely on tertiary sources.
• SIMATIC S7-1200 product page — firmware downloads, FAQ, application examples, and engineering tools.

FAQ