S7-1200 Cyclic OB Replacement for S7-200 INT0/INT1/INT2 Events

S7-1200 Cyclic OB Replacement for S7-200 INT0/INT1/INT2 Events

Migrating programs from a SIMATIC S7-200 to a SIMATIC S7-1200 forces a redesign of the interrupt structure. The S7-200 used the ATCH (attach) and DTCH (detach) instructions to bind integer event numbers (Event 10 = Timed interrupt 0; Event 24 = Port 1 receive complete; Event 26 = Port 1 transmit complete) to local subroutines. The S7-1200 does not retain this exact event-table model. Instead, it relies on Organization Blocks (OBs) combined with the time-delay instructions SRT_DINT, CAN_DINT, and QRY_DINT, plus edge-triggered programming on the RCV_PTP and XMT_PTP instruction status bits. This reference walks through each replacement, then provides a TIA Portal configuration procedure, timing analysis, and verification checklist.

1. S7-200 Interrupt Model Recap

The S7-200 CPU 22x family executed subroutines attached to fixed hardware and timer events using the ATCH instruction. The event numbers relevant to this migration are:

The S7-200 stored the time-base for Event 10 in SMB34 (1-255 ms) and Event 11 in SMB35. A single ATCH INT_x, EV_y call bound the event to a subroutine. The same model is not exposed on the S7-1200.

2. S7-1200 Organization Block Model

The S7-1200 uses Type 30 Cyclic OBs, Type 20 Time-Delay OBs, Type 10 Time-of-Day OBs, and Type 40-47 Hardware interrupt OBs. Each OB can be created in TIA Portal under Program Blocks → Add new block → Organization Block with the chosen type.

The S7-1500 differs from the S7-1200 in one detail discussed in field practice: on the S7-1500 the cyclic OB cycle time is set in microseconds, while on the S7-1200 it is set in milliseconds. A 10 ms cycle therefore requires 10000 on S7-1500 and 10 on S7-1200. Verify the unit shown in TIA Portal for the target platform before commissioning.

3. Mapping Timed Interrupts (S7-200 Event 10 → S7-1200 SRT_DINT)

The S7-200 Event 10 / SMB34 pair implemented a free-running periodic interrupt. Two distinct replacement paths exist on the S7-1200:

3.1 Cyclic Interrupt OB30 (preferred for true periodic behavior)

A Cyclic OB runs automatically once per configured interval without any instruction invocation. The CPU is responsible for the timekeeping, eliminating the scan-time-dependent drift seen with SRT_DINT.

1. In the TIA Portal project tree, expand Program Blocks.
2. Double-click Add new block → choose Organization Block.
3. Type = Cyclic interrupt; OB number = e.g. OB30.
4. Open the OB properties, set Cycle time in ms (range and granularity is firmware-dependent; see S7-1200 System Manual).
5. Optionally set a Phase offset to shift the OB start relative to OB1 cycle begin.

3.2 Time-Delay OB20 + SRT_DINT (for one-shot delays)

When the original code used SMB34 as a one-shot countdown rather than a periodic trigger, OB20 is the correct replacement. The SRT_DINT instruction arms the OB; after DTIME elapses, OB20 executes once.

SRT_DINT signature

Example ST / SCL call in OB1

// SRT_DINT instance stored in a global DB or multi-instance
#iRet := "db_TimeDelay".SRT_DINT_1(REQ := bStartDelay,
                                    DTIME := tDelayValue,
                                    SIGN := W#16#0001);
IF #iRet <> 0 THEN
    // Handle error - see TIA Portal online help for RET_VAL mapping
END_IF;

Companion instructions

• CAN_DINT: cancels a pending time-delay interrupt before it fires. Useful when an external condition makes the delayed action obsolete.
• QRY_DINT: queries the current status of OB20 (idle / running / expired). Returns STATUS, ACK, etc.

4. Mapping Serial Receive Complete (S7-200 Event 24 → S7-1200 RCV_PTP)

On the S7-200, Event 24 fired after RCV finished filling its receive buffer. The S7-1200 has no analogous OB. Instead, RCV_PTP (or Receive_P2P in legacy variants) provides status outputs that are evaluated cyclically.

RCV_PTP status outputs

The recommended pattern is:

1. Call RCV_PTP from OB1 (or a cyclic OB) with EN_R tied to a true condition so the instruction is always armed.
2. Detect a rising edge of the NDR output.
3. On that edge, copy the receive buffer to working memory and call the processing FB/FC.

// Rising-edge capture of RCV_PTP.NDR
#rcvDonePulse := "ptpCtrl".RCV_PTP_1.NDR AND NOT #rcvDonePrev;
#rcvDonePrev := "ptpCtrl".RCV_PTP_1.NDR;
IF #rcvDonePulse THEN
    "ProcessRxFrame"(LEN := "ptpCtrl".RCV_PTP_1.LEN);
END_IF;

This produces behavior equivalent to a dedicated receive interrupt. If the OB1 scan is too slow relative to the data rate, move the RCV_PTP call into a Cyclic OB running at 1-5 ms to reduce event-to-action latency.

5. Mapping Serial Transmit Complete (S7-200 Event 26 → S7-1200 XMT_PTP)

Event 26 fired once the XMT buffer was sent. On the S7-1200, XMT_PTP offers a DONE output that pulses TRUE for one scan on successful transmission, plus ERROR and STATUS. Trigger downstream actions the same way as for NDR:

#xmtDonePulse := "ptpCtrl".XMT_PTP_1.DONE AND NOT #xmtDonePrev;
#xmtDonePrev := "ptpCtrl".XMT_PTP_1.DONE;
IF #xmtDonePulse THEN
    // Queue next frame, update handshake flags
END_IF;

6. Hardware Interrupt OBs (OB40-OB47)

For S7-200 Events 0-7 (digital-input rising/falling edges), the S7-1200 uses Hardware Interrupt OBs. Configuration steps:

1. Open the CPU Device Configuration in TIA Portal.
2. Select the digital input channel used for the trigger.
3. Enable the Hardware interrupt check box.
4. Add OB40 (or any OB40-OB47) under Program Blocks.
5. Wire the OB to the input channel via the Event list (drag the OB onto the trigger row).

Inside OB40 the start info block OB40_POINT_ADDR contains the hardware identifier of the triggering input, allowing a single OB to handle multiple channels through a tag compare.

7. Step-by-Step TIA Portal Configuration

7.1 Prerequisites

• TIA Portal V15 or newer (use a version compatible with the target CPU firmware).
• S7-1200 CPU ≥ firmware 4.0 for full OB30 / OB20 support (older firmware may restrict cycle-time granularity).
• Signal Module or onboard serial port if migrating Event 24/26 paths.
• S7-1200 System Manual — see SIMATIC S7-1200 System Manual.

7.2 Procedure

1. Create the cyclic OB: Project tree → Program Blocks → Add new block → Organization Block, type Cyclic interrupt. Set the cycle time in ms. For network and PtP tasks, 5 ms is a stable starting point; for fast HSC/PTO coordination, 1-2 ms is acceptable on CPUs with sufficient headroom.
2. Create the time-delay OB: Repeat the above for Time-delay interrupt (OB20).
3. Create hardware interrupt OBs for any input-edge triggers required (OB40-OB47).
4. Replace ATCH calls: In OB1, delete the old ATCH INT, EV statements. Convert periodic Event 10 logic into OB30 code. Convert Event 24 logic into the NDR rising-edge evaluation.
5. Insert SRT_DINT instances: In a new global DB or as multi-instances inside an FB, instantiate SRT_DINT, CAN_DINT, and QRY_DINT per requirement.
6. Compile and download: Mark all new/modified blocks and download. After download, perform a STOP→RUN transition.
7. Verify in online mode: Right-click the OB and select Monitor & force. Confirm the call count increments at the expected rate.

8. Timing Analysis: Scan Time, OB Latency, and Edge Cases

Three latency terms govern S7-1200 interrupt response:

1. Event-to-OB latency — hardware event detection to OB start. For hardware OBs this is firmware-deterministic; for cyclic OBs it is governed by the configured phase offset.
2. OB execution time — duration of the OB body. Long OBs delay OB1 and degrade cyclic scheduling.
3. OB1 cycle time — total scan. Heavy use of SRT_DINT with very small DTIME values can stack events faster than OB20 can complete, causing late execution. The firmware buffers only a limited number of OB20 entries.

8.1 Choosing cycle times

9. Memory and Work Memory Considerations

Adding OBs, instance DBs for the time-delay instructions, and RCV_PTP/XMT_PTP data buffers increases the work-memory footprint. Field cases show small S7-1200 CPUs (e.g., CPU 1214C) saturating the work memory near 99 % when the legacy S7-200 ladder is converted one-to-one. Mitigation:

• Use multi-instance DBs for FBs containing the interrupt instructions to avoid one DB per instance.
• Delete unused S7-200 library blocks and helper subroutines.
• Consolidate cyclic OBs where multiple periodic rates share code.
• Upgrade to a CPU with larger work memory if the percentage loaded exceeds ~85 % after the migration — CPU headroom under 15 % leaves little room for diagnostics and online changes.

10. Verification Procedure

1. Online → Monitor & force the relevant OB; confirm Call count increments at the configured interval.
2. For time-delay interrupts, add a temporary tag inside OB20 and force-toggle a DO; confirm timing with a high-speed counter or external logic analyzer.
3. For serial events, loop back TX→RX at the wiring panel; verify the NDR pulse fires once per received frame and the processing FB executes.
4. Force ERROR conditions (e.g., wrong parity) and confirm the ERROR/STATUS outputs reach OB1 logic.
5. Measure OB1 scan time before and after the new OBs are loaded; confirm no regression in main-cycle performance.
6. Cycle power to the CPU and re-verify that all OBs re-arm automatically (cyclic and time-of-day should; OB20 must be re-started via SRT_DINT).

11. Common Pitfalls

12. Frequently Asked Questions