S7-1200 High-Speed Counter Limit: 6 HSC Maximum Workarounds

Overview

The SIMATIC S7-1200 controller family supports a maximum of six high-speed counters (HSC1 through HSC6) per CPU. This is a firmware-enforced ceiling that applies to every CPU variant in the S7-1200 range, including the compact CPU 1211C, the mid-range CPU 1212C, CPU 1214C, CPU 1215C, and the high-frequency CPU 1217C. The limit cannot be raised by installing additional Signal Boards (SB), digital input (DI) modules, or digital input/output (DI/DO) signal modules on the right-side expansion port. The ceiling is bound to the onboard logic of the CPU image and cannot be extended in TIA Portal by selecting additional HSC numbers.

Engineers who require more than six incremental encoders or pulse sources on a single logical controller must therefore select from a small set of alternatives: software-based counting on standard digital inputs using cyclic or hardware interrupts, distribution of encoders across multiple networked S7-1200 CPUs, the use of LOGO! 8 base modules as remote counters over Ethernet, or the deployment of dedicated counter modules on distributed I/O stations such as SIMATIC ET 200SP or ET 200MP.

S7-1200 HSC Architecture and Resource Allocation

Each HSC instance occupies dedicated onboard or SB digital inputs that are hard-mapped to specific counters. TIA Portal enforces the relationship between input terminals and HSC instances. The HSC channel selection list in the device configuration (CPU Properties → High-speed counters) exposes exactly six HSC instances with predefined input assignments per CPU variant.

HSC Counting Modes and Maximum Input Frequencies

The S7-1200 HSC supports several counting modes selectable per instance. Mode selection determines how the encoder pulses are decoded and influences the effective pulse rate at the input terminal. Quadrature 4x evaluation multiplies the input pulse rate by four, which can saturate the 100 kHz ceiling even at modest encoder shaft speeds.

Maximum input frequency per HSC instance depends on the CPU model and the input source:

Why the Six-HSC Limit Cannot Be Expanded Onboard

The S7-1200 HSC engine is implemented in the CPU's dedicated counter hardware block. Each HSC instance consumes a fixed resource pair: one or two dedicated high-speed input channels plus a hardware counter register. The firmware exposes six such resources, and they cannot be reallocated through SB, SM (signal module), or CP (communication processor) expansion.

Attempting to configure additional HSC instances in TIA Portal beyond HSC6 yields the message "No HSC available" or removes the option from the selection list. Adding a SB 1221 DI4 module only provides additional digital inputs usable as HSC inputs if a free HSC instance number (1–6) is still available; the SB does not introduce a seventh HSC engine. Likewise, an SM 1221 digital input module cannot serve as HSC inputs because SM inputs are scanned by the standard image and lack the hardware connection to the HSC engine.

This design choice is documented in the SIMATIC S7-1200 Programmable Controller System Manual, which explicitly states the maximum number of HSC instances per CPU.

Alternative 1 — Software Counters on Standard Digital Inputs

Standard digital inputs (DI from onboard, SB, or SM modules) can be used to implement software counters using the cyclic OB1 scan, hardware interrupts on the rising/falling edge of a DI, or timed interrupts. This approach extends the counting capacity beyond six channels without requiring additional hardware, but it is limited by the input filter time and the OB execution time.

Method A — Hardware Interrupt Counting

Attach a hardware interrupt OB (OB40) to the DI used as the pulse input. Each rising edge increments a counter tag in a global DB. The maximum countable frequency is governed by the input filter (configurable from 0.1 ms to 20 ms in TIA Portal) and the OB40 execution latency.

Approximate maximum count rate with a 0.1 ms digital input filter:

For a 0.1 ms filter and a 100 µs OB40 latency, expect ~5,000 pulses/s as a practical limit. The CPU 1211C/1212C require a longer filter due to the input acquisition scan. Always validate on the target hardware before deployment.

Method B — Timed Interrupt Counting

A cyclic timed interrupt OB (OB30–OB38) can sample a standard DI at a configurable interval (1 ms to 60 s in TIA Portal). The interrupt handler reads the DI state and increments or decrements a counter tag accordingly. This method supports up to ~1 kHz with a 1 ms OB30 cycle on a lightly loaded CPU, which is sufficient for encoders under 50 Hz A/B quadrature as described in the source application.

Alternative 2 — Distribute Encoders Across Multiple S7-1200 CPUs

When the application requires more than six incremental encoders with full hardware counting reliability, the most pragmatic S7-1200-native approach is to use two or more S7-1200 CPUs networked over PROFINET or Industrial Ethernet, with each CPU handling up to six encoders. The host CPU aggregates the count values from the partner CPU via PUT/GET, TSEND/TRCV, or PROFINET I-device data exchange.

Configuration Procedure

1. Add the second S7-1200 CPU to the TIA Portal project as a separate device.
2. Configure HSC1–HSC6 on each CPU according to encoder count.
3. Establish an Ethernet connection between the two CPUs.
4. In the host CPU's program block, add PUT instructions to read the partner CPU's HSC count DB or use the simpler TSEND_C/TRCV_C pair on ISO-on-TCP connections (port 2000).
5. Enable PUT/GET access on the partner CPU under Properties → Communication → Access to the PLC.
6. Update the HSC count value at a rate appropriate to the application (typically 10–100 ms).

Two CPU 1215C units can therefore serve up to 12 incremental encoders while remaining within the S7-1200 product line. PROFINET IRT is not required; standard PN RT communication is sufficient for counter aggregation.

Alternative 3 — LOGO! 8 Base Module as a Remote Counter

The LOGO! 8 base module (BM) includes four high-speed digital inputs (I3, I4, I5, I6) that operate as up/down counters at up to 5 kHz. Each LOGO! BM can therefore supply four counters and can be networked to the S7-1200 as an Ethernet participant using the LOGO! Access Tool or the S7 communication PUT/GET mechanism (LOGO! 8 BM supports S7 communication from firmware version FS04 onward).

For applications with encoders below 50 Hz A/B quadrature, the 5 kHz capability of the LOGO! 8 BM is comfortably sufficient. One S7-1200 CPU combined with two LOGO! 8 BM modules can serve 6 (onboard HSC) + 4 + 4 = 14 counter channels, each fully hardware-backed.

Alternative 4 — Distributed I/O with Dedicated Counter Modules

For higher count rates (above 100 kHz) or for applications where a single logical controller is mandated, deploy a distributed I/O station with a dedicated counter module. The S7-1200 CPU can communicate as the PROFINET IO controller with an ET 200SP or ET 200MP station that hosts a counter module.

Each TM PosInput 2 module adds two counter channels without consuming any of the six onboard HSC instances. Multiple modules can be deployed on a single ET 200SP station up to the PROFINET slot limit (typically 64 modules per IO controller). This is the recommended path when the S7-1200 must remain the single CPU and encoder count exceeds six.

Alternative 5 — External Standalone Counter Hardware

For installations where encoder count, PROFINET availability, or speed requirements exceed what S7-1200-class CPUs can absorb, consider third-party standalone counters that publish data via Modbus TCP, EtherNet/IP, or PROFINET. Devices such as the Wachendorff WDG series with Ethernet gateway, IFM AL1342, or Balluff BUS0027 provide multi-channel counting in industrial housings and present the data as cyclic PROFINET IO. The S7-1200 can consume this data without using any of its six HSC instances.

Quadrature Encoder (A/B) Specific Considerations

When A/B quadrature encoders are involved, the HSC's mode setting determines the count multiplier:

• 1x evaluation: counts once per A-channel rising edge. Maximum input frequency = max count rate.
• 2x evaluation: counts on each A-channel edge. Maximum input frequency / 2 = max shaft pulse rate.
• 4x evaluation: counts on every A and B edge. Maximum input frequency / 4 = max shaft pulse rate.

For encoders < 50 Hz shaft speed with 1,024 ppr (pulses per revolution), the resulting 4x quadrature count rate is approximately 200 kHz. This exceeds the 100 kHz HSC ceiling on CPU 1214C/1215C and would saturate HSC1–HSC4 on CPU 1217C at 1 MHz. The application described in the source (< 50 Hz, unspecified ppr) is compatible with the 6-HSC budget assuming standard ppr ratings. For > 6 encoders with similar speed/ppr profile, the two-CPU distribution or TM PosInput approach is recommended.

Selection Matrix — Choosing the Right Expansion Method

Commissioning and Verification Procedure

1. In TIA Portal, navigate to CPU Properties → High-speed counters and confirm that no more than six HSC instances are assigned to inputs. Verify the input terminal assignment matches the wiring diagram.
2. Place a CTRL_HSC instruction block in the user program and connect it to the HSC instance. The CTRL_HSC_EXT extended instance provides additional parameter access.
3. Enable Access to the PLC via PUT/GET communication on any partner CPU before commissioning networked alternatives.
4. Rotate each encoder through a known displacement (e.g., 1,000 pulses) and verify the HSC count reads exactly 1,000 × evaluation multiplier.
5. For quadrature encoders, rotate in both directions and verify the HSC direction status bit transitions correctly.
6. For distributed alternatives, exercise the network update cycle (PUT/GET, TSEND/TRCV) and verify the host CPU sees count updates at the expected rate.
7. Capture diagnostic buffer entries during commissioning to confirm no HSC overflow or input filter warnings are logged.

Troubleshooting Matrix

FAQ