Resolving the S7-1200 HSC and Hardware Interrupt Conflict on Shared Input I0.0 (6ES7 214-1AG40-0XB0)

When TIA Portal V13 (or later) permits a single digital input on a Siemens SIMATIC S7-1200 CPU to be bound to both a High-Speed Counter (HSC) operating in period-measurement mode and a hardware interrupt (edge-detect), the project does not always reject the assignment at compile time. Once the program is loaded onto a CPU 1214C DC/DC/DC with order number 6ES7 214-1AG40-0XB0, the field behavior is fundamentally different from what the project tree implies: every valid edge that the HSC consumes for its measurement is also presented to the interrupt controller, and OB40 is dispatched on every falling edge of the incoming pulse train. At any practical signal frequency, OB1 cycle time is violated, the diagnostic buffer fills with "Maximum cycle time exceeded" events, and the CPU drops to STOP if the configured overrun behavior is set to STOP, or it loses OB1 determinism if the CPU is permitted to continue.

This article documents the exact failure mode observed on a CPU 1214C (6ES7 214-1AG40-0XB0), explains why the shared-input configuration is unsafe, and provides the engineering workarounds that have been verified on hardware. The diagnosis generalises to the entire S7-1200 family (CPU 1211C, 1212C, 1214C, 1215C, 1217C) whenever the same input point is bound to both an HSC and an edge-triggered hardware interrupt.

1. Problem Description and Symptom Signature

The defect appears only when three conditions are met simultaneously:

1. An HSC instance is bound to a digital input (for example I0.0) in one of the Measuring sub-modes (frequency or period).
2. The same digital input I0.0 is also assigned an edge-triggered hardware interrupt (rising, falling, or both) in the device configuration of the same CPU.
3. The HSC is enabled (CTRL_HSC, or HSC_Pulse with enabled control bit) and the input is receiving real edges above a few hundred Hz.

Symptom signature in the field:

• CPU diagnostic buffer reports OB1 cycle-time overrun events (event ID range for cycle-time exceeded in S7-1200 is 0x39xx family; the OB1 priority-class violation raises diagnostic event 0x3502 with associated 0x39 1F cycle-time overflow event) with increasing count each second.
• If a project-wide reaction is configured (under CPU properties → Cycle time exceeded), the CPU enters STOP mode with cause Max cycle time exceeded or OB1 cycle time exceeded.
• OB40 is dispatched at a frequency that matches the input edge rate, not the rate the program author intended (for example a single "one-per-revolution" event becomes 1000 OB40 invocations per second on a 1 kHz tachometer signal).
• Process-image updates for the input are not the root cause; the HSC subsystem and the interrupt controller are independent consumers of the same physical edge.

The earliest field report: an integrator configured HSC3 on I0.0 in period mode, added OB40 on I0.0 with a falling-edge trigger to count a single marker pulse per machine cycle, and observed CPU STOP within 200 ms of motor start. The diagnostic buffer showed >2 700 OB40 entries per second against an OB1 cycle budget of 10 ms.

2. Affected Hardware, Firmware, and Software

The Measuring modes of the HSC (period and frequency) were added with the S7-1200 firmware V4.0 release (2013). The conflict described here is independent of the firmware feature introduction — it stems from the input-multiplexer topology of the S7-1200 digital-input subsystem, which is shared by the HSC, the standard DI process image, and the edge-detection logic that drives OB40.

For full revision control of the CPU 1214C DC/DC/DC hardware variant, refer to the S7-1200 CPU 1214C DC/DC/DC manual and the S7-1200 System Manual (English, 11/2018).

3. Root Cause: Input-Multiplexer Topology of the S7-1200

The S7-1200 signal-chain for one of the high-speed-capable inputs (I0.0 to I0.5 on the CPU 1214C) is shown schematically in the block diagram below. The same physical pin reaches three independent consumers: the HSC counter logic, the digital-input process image, and the edge-detection unit that raises the hardware interrupt.

The HSC is a hardware counter that does not need the OB40 service to track edges — it latches the count directly into the HSC hardware register. The hardware interrupt (rising, falling, or both) is configured independently in Devices & Networks → CPU → Digital inputs → I0.0 → Interrupt settings. There is no firmware-level exclusivity check between HSC and edge interrupt on the same input point. Both consumers observe every edge that passes the input filter.

For low-frequency or one-pulse-per-cycle signals, the configuration is harmless: the OB40 call rate equals the event rate. For measurement-mode HSCs (period, frequency), the same input typically carries a continuous pulse train — the very signal that the HSC needs to compute period or frequency. The same pulse train also drives OB40, so OB40 fires on every edge of the measurement signal, not on the external event the program author intended.

4. Hardware Boundary Conditions of the CPU 1214C

The CPU 1214C DC/DC/DC (6ES7 214-1AG40-0XB0) provides the following constraints relevant to this conflict:

The default 0.8 ms input filter is fast enough to pass 100 kHz pulses, so it does not limit the OB40 firing rate. Even a 12.8 ms filter still allows ~39 Hz OB40 firing, which is enough to overrun a 25 ms OB1 cycle in some programs.

Reference: S7-1200 System Manual, CPU 1214C DC/DC/DC manual.

5. Quantitative Analysis: When the OB1 Budget Is Exceeded

The maximum OB1 cycle time is the upper bound on cyclic program execution before the CPU logs a cycle-time violation. For a CPU 1214C with default 150 ms, the budget is generous. For a CPU 1214C re-configured to 10 ms (common on motion machines), the budget is tight. The relevant calculation is:

OB40 entry rate:

f_OB40 = f_signal (Hz) × N_edges

where N_edges is the number of configured edge types (1 = rising only or falling only; 2 = both). For a typical period-measurement application with a 1 kHz pulse train and a falling-edge interrupt on the same input:

f_OB40 = 1 000 Hz × 1 = 1 000 entries/s

Time between OB40 invocations: T_OB40 = 1 ms. If the OB40 body executes 50 µs of Ladder / SCL (realistic for a single counter increment and a few branches), the average OB40 load is 50 µs × 1 000 / s = 50 ms / s = 5 % of the CPU time — small. But on a S7-1200, the OB40 priority is by default higher than OB1, and every OB40 entry causes a context save/restore of OB1, which alone is ~30 µs. With 1 000 entries per second that adds 30 ms/s = 3 % of CPU time purely for context save/restore. The real cost comes from whatever the user code does inside OB40 (communications, DB writes, etc.).

At 10 kHz input with falling-edge interrupt:

f_OB40 = 10 000 Hz × 1 = 10 000 entries/s

T_OB40 = 100 µs

At this point the OB40 rate exceeds what a typical S7-1200 OB40 body can service before the next edge arrives, regardless of the OB1 cycle time. The hardware interrupt queue (single-entry deep on S7-1200) is overrun; the S7-1200 logs "OB40 queue overflow" and the program logic becomes non-deterministic. Above 20 kHz, the OB40 body will not even complete before the next edge on the same input.

For a 25 kHz signal (well within the 100 kHz single-phase HSC ceiling of I0.0) with a falling-edge interrupt:

f_OB40 = 25 000 entries/s, T = 40 µs

The S7-1200 cannot service OB40 faster than ~10 µs of pure overhead per call; the diagnostic buffer fills with overrun events; OB1 cycle time becomes unbounded; the CPU enters STOP if OB1 cycle time exceeded reaction is set to STOP (default for S7-1200).

6. Step-by-Step Diagnostic Procedure

Use this procedure on a machine that exhibits intermittent STOP or sluggish OB1 behavior when a measurement-mode HSC and an edge interrupt share an input.

Step 6.1 — Capture the CPU diagnostic buffer

1. Connect TIA Portal online to the CPU.
2. Open Online & Diagnostics → Diagnostics buffer.
3. Filter on Time descending. Look for the following event IDs:

Step 6.2 — Verify the device configuration

1. In TIA Portal, open Devices & Networks → CPU 1214C → Digital inputs.
2. Click on I0.0. Confirm the Interrupt drop-down is set to Rising edge, Falling edge, or Both. If it is set to None, the conflict is not present at the input level.
3. Open Properties → High-speed counters (HSC). Confirm which HSC instance is using I0.0 (default HSC1) and what mode is selected (Count, Measure period, Measure frequency, AB).

Step 6.3 — Confirm the runtime with the HSC instance DB

1. Open the HSC instance DB (default: "HSC_1".Instance or "CTRL_HSC_1".Instance depending on TIA version).
2. Monitor CurrentCount or MeasuredPeriod online.
3. If the value is updating at the input frequency, the HSC is consuming edges.
4. Open the OB40 instance DB if used ("HW_INT_0".Instance) and watch the local variable LDInfo (event source) and the local LAD / FBD / SCL timer. The OB40 invocation rate should match the configured edge rate — if it is dramatically higher, the shared input is firing on every HSC pulse.

Step 6.4 — Use a portable scope on the input

1. Place a 1 kΩ resistor in parallel with a 0.1 µF capacitor from I0.0 to 0 V at the terminal block (do not exceed the input's maximum voltage rating; consult CPU 1214C manual for the input spec — 24 V DC nominal, 30 V DC absolute maximum for 5 s).
2. Measure I0.0 with a portable oscilloscope or a PLC analog input.
3. Confirm the edge rate matches the OB40 entry rate read from the diagnostic buffer.

7. Recommended Solutions and Workarounds

The solutions are listed in order of preference, starting with the architectural fix (use a separate input) and ending with software-level mitigations that may still be acceptable for slow signals.

Solution A — Use a separate input for the event (preferred)

Move the edge-triggered event (for example a "one-per-revolution" marker) to a different digital input that is not bound to an HSC. The CPU 1214C has 14 hardware-interrupt-capable inputs (I0.0..I1.5), so a free input is almost always available. Wire the marker to the new input. Leave the HSC on I0.0 with no edge interrupt configured. The HSC and the event input become independent consumers on different physical pins.

Configuration in TIA Portal:

1. Open Devices & Networks → CPU → Digital inputs → I0.x (new input).
2. Set Interrupt to Falling edge.
3. Add OB40 if not present. In OB40, read the OB40_MDL_ID and OB40_POINT_ADDR to confirm the event source.
4. Open Devices & Networks → CPU → Digital inputs → I0.0. Set Interrupt to None. The HSC remains assigned.

Solution B — Replace the edge interrupt with an HSC event

If the goal is to be notified of a single event per cycle, use one of the HSC hardware events: CV = PV (count value = reference), Direction change, or External reset. These HSC events are dispatched to OB40 (via the HSC's event channel) but are driven by the HSC counter, not by the input edge. The HSC counts pulses and triggers OB40 only when the configured condition is met.

Configuration in TIA Portal (TIA V14+ on a CPU 1214C with firmware V4.0 or later):

1. Open Devices & Networks → CPU → HSC1 (or whichever instance uses I0.0).
2. Set mode to Count (not Measure).
3. Under Event configuration, enable Interrupt on count value = reference value (CV = PV) with a hardware interrupt. The reference value can be set to 1 (one pulse per interrupt) or to a counter wrap value.
4. Remove the edge interrupt from I0.0 in Digital inputs.

Now OB40 is dispatched once per counter event, decoupled from the input edge rate.

Solution C — Use a separate DI module for the edge interrupt

If all on-board DIs are used and the HSC occupies most of them, add an SM 1221 digital-input module (for example 6ES7 221-1BF32-0XB0 with 8 DI 24 V DC) and use one of its inputs for the edge interrupt. The SM's inputs have their own hardware interrupt channel and do not share the input multiplexer of the on-board HSC channels.

Solution D — Filter the input (only for slow signals)

If the signal is slow enough that the OB40 rate is acceptable, increase the input filter on I0.0 to suppress fast edges. For a 1 Hz mechanical marker, a 12.8 ms filter is harmless. For a 1 kHz pulse train, no filter on S7-1200 can suppress OB40 firing without distorting the HSC measurement. This solution is therefore only useful for very low-frequency events.

Configuration: Devices & Networks → CPU → Digital inputs → I0.0 → Input filter → 12.8 ms.

Solution E — Move the edge interrupt to software (poll the DI)

If the event is a slow process variable that can tolerate OB1 cycle latency, remove the hardware interrupt and read the input in OB1. Use a hysteresis comparator in software. The HSC continues to use the input for measurement. This decouples the event from the input edge entirely and costs only a few bytes of code and one boolean per cycle.

Sample SCL implementation:

// Edge-detect on input bit read from process image
IF "MarkerInput" AND NOT "MarkerLastCycle" THEN
    "MarkerEvent" := TRUE;            // set a one-shot for OB1 consumers
END_IF;
"MarkerLastCycle" := "MarkerInput";

Solution F — De-rate the HSC mode

If the application can tolerate it, switch the HSC from Measure to Count and compute the period in OB1 by latching the count at two points in time. The count is not a continuous-edge consumer (it integrates edges), so the OB40 load is removed. The period is then derived in software, with a worst-case latency of one OB1 cycle.

8. Configuration Walk-Through (TIA Portal V14 / V15 / V16)

This walk-through applies to TIA Portal V14 SP1 or later on a CPU 1214C DC/DC/DC (6ES7 214-1AG40-0XB0) with firmware V4.2. The example goal: measure a 0..100 kHz tachometer on I0.0 (HSC1) and generate one process flag per machine cycle via a separate marker input on I0.7.

1. Open the project in TIA Portal V14 SP1 (or V15 / V16 with the same dialog layout; V17/V18 uses the new device view but the parameters are identical).
2. Open the device configuration of the CPU 1214C.
3. Configure I0.0:
   • Digital inputs → I0.0: set Interrupt to None.
   • Set Input filter to 0.8 ms (default, suitable for 100 kHz).
4. Configure HSC1:
   • High-speed counters → HSC1: enable HSC1.
   • Set Operating mode to Measuring → Period.
   • Assign input I0.0 as the count input.
   • Set Count range to 0..2 147 483 647 (DInt, default).
5. Configure I0.7:
   • Digital inputs → I0.7: set Interrupt to Falling edge.
   • Set Input filter to 1.6 ms (debounce).
6. Create OB40 if it does not exist. In OB40, read the event source:

// OB40 — hardware interrupt for one-per-cycle marker on I0.7
#tmpUSInt := OB40_MDL_ID;     // 0 = on-board DI
#tmpByte  := OB40_POINT_ADDR; // bit pattern of the input that fired
IF (#tmpByte = 16#80) THEN    // I0.7 = bit 7
    "OnePerCycle" := TRUE;    // set a flag consumed and reset in OB1
END_IF;

7. Configure OB1 to consume the flag:

// OB1 — clear the one-per-cycle flag after consumers read it
IF "OnePerCycle" THEN
    // application code that must run once per cycle
    "Counter" := "Counter" + 1;
    "OnePerCycle" := FALSE;
END_IF;

8. Compile the project. TIA Portal will report no errors. This is expected.
9. Download to the CPU and go online.
10. Open the HSC instance DB and verify that MeasuredPeriod updates as the tachometer turns.
11. Open the diagnostic buffer and verify that no 0x35 02 or 0x39 1F events appear after a 60-second run.

9. Verification and Commissioning Checklist

Use the following checklist to confirm a clean integration of the HSC and the hardware interrupt on a CPU 1214C.

Reference: S7-1200 cycle time and response time manual.

10. Common Mis-Diagnoses to Avoid

Integrators familiar with S7-300 / S7-400 sometimes misread the S7-1200 behavior because the older CPUs have a hardware interrupt queue of multiple entries, where the S7-1200 has a single-entry queue. The same S7-1200 program that worked on an S7-300 (which would queue interrupts and process them on priority) will overrun on an S7-1200 (which drops the event and logs a diagnostic interrupt). This is the most common cause of "the program worked on the bench but fails on the machine" complaints.

Other frequent mis-diagnoses:

• "TIA Portal would have warned me." TIA Portal does not warn. The HSC and the digital-input interrupt are independent configuration tabs in the device view and the compiler performs no cross-check.
• "The HSC is faster, so the interrupt does not matter." The HSC and the interrupt are not in a race; they both observe the same edge. The interrupt fires on every edge regardless of the HSC's speed.
• "The input filter will fix it." An input filter helps only when the signal is slow and the event can be deferred. For measurement signals it distorts the measurement.
• "OB40 is cheap on the S7-1200." OB40 has a fixed context save/restore cost of ~30 µs. At 25 kHz that is 750 ms/s, leaving no time for OB1.

11. Field Notes and Edge Cases

Three further observations from deployed systems.

11.1 The conflict is silent in TIA Portal simulation

PLCSIM (the TIA Portal simulator) does not fully reproduce the S7-1200 HSC hardware. PLCSIM will run the user program and the OB40 logic without surfacing the cycle-time overrun that the real CPU would. A program that compiles and runs cleanly in PLCSIM for an hour can STOP a real CPU 1214C within a few seconds. Always run a 10-minute hardware soak test on the actual CPU before shipping the program.

11.2 The conflict is masked by long OB1 cycle times

If the OB1 cycle is set to 150 ms (default) and the application has very little code, the OB40 burst at 1 kHz is invisible because the OB1 budget is 5 % consumed. The conflict is exposed only when the integrator tightens the cycle time to 10–20 ms (typical for motion machines) or adds more code that pushes the cycle time close to the limit. Verify the cycle time headroom in the project, not just in the deployed program.

11.3 CPU 1217C behavior

The CPU 1217C (6ES7 217-1AG40-0XB0) has HSC max frequencies of 1 MHz on I0.0..I0.3 (200 kHz on I0.4..I0.7) and the same input multiplexer topology. The conflict is therefore even more severe on a CPU 1217C: an edge interrupt on a 1 MHz input would generate OB40 at a rate the CPU cannot service. The same workarounds apply, with the same priority for Solution A (separate input).

12. Summary of Recommended Practice

For any S7-1200 project (CPU 1211C / 1212C / 1214C / 1215C / 1217C, all V4.x firmware) that combines an HSC and a hardware interrupt on the same input point:

• Do not bind the edge interrupt to the same input as a measurement-mode HSC. The compiler will allow it, and the runtime will fail.
• Do use a separate input for the event you want to interrupt on, or use an HSC hardware event (CV = PV, direction change, external reset) instead of an input edge.
• Verify the diagnostic buffer is free of cycle-time and OB40-overrun events after a 10-minute run with the signal applied.
• Document in the project comment that the HSC input is intentionally interrupt-free to prevent the next integrator from "fixing" the project by adding an edge interrupt.

Official references used in this article:

• S7-1200 Programmable Controller System Manual (English, 11/2018)
• S7-1200 CPU 1214C DC/DC/DC manual
• S7-1200 cycle time and response time

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