S7-1200 HSC Quadrature Encoder Wiring and Grounding Fix

Problem Description: Skipped HSC Counts and Quadrature Drift on CPU 1212C

A CPU 1212C AC/DC/RLY connected to a Koyo TRD-N60-RZWD incremental rotary encoder (quadrature output, 25% phase difference, 4.75–40 VDC supply) is configured for HSC1 in AB Quadrature 1X mode with hardware inputs A = I0.0, B = I0.1. On a hand-turned encoder the count does not increment evenly: clockwise rotation produces count = 1, then jumps to 3, then 4, then 5, then 7. Returning the shaft 1800° clockwise and then back 1800° counter-clockwise does not return the count to zero — the counter ends in negative values, indicating missed pulses in one direction and asymmetric counting in the other.

The user observed that the HSC mechanism itself does count (ID1000 updates on each pulse), which proves that the HSC is enabled, the input filter is open, and the wiring is electrically reaching the module. The defect is therefore not in the HSC logic; it is in the analog integrity of the input signal at the PLC terminals.

After systematic trial, the root cause was identified as a missing ground reference between the PLC's M terminal (input bank common) and the encoder's 0V return. Adding a jumper from the PLC ground to the input bank common eliminated the noise, and the count returned to a clean ±1 increment per quadrature transition.

Root Cause: Floating PLC Input Bank and Encoder Common

On a Siemens S7-1200 DC-type input bank, each digital input is referenced to the 1M terminal of its input group. If the encoder's 0V (BLU wire on the TRD-N60-RZWD) is tied to one supply rail and the PLC's 1M is left floating or tied to a different reference, the input threshold comparator can drift through the encoder's logic-low region. Each time the input voltage hovers near the threshold, the HSC sees extra edges, and quadrature decoding interprets them as direction-dependent transitions. This produces the classic signature:

• Counts increment when the shaft turns one way (the rising edges are clean), but count backwards or skip when the shaft reverses (one channel's edges fall into the threshold band).
• Long-term drift: rotate N turns CW, then N turns CCW — counter does not return to zero.
• Counting "feels right" at low speed but degrades as the input filter engages or as common-mode voltage changes with cable routing.

The TRD-N60-RZWD open-collector / push-pull output stage requires a defined 0V return path. The PLC must provide it, and the encoder's BLU wire must land on the same 0V potential as the PLC's 1M terminal. On an AC/DC/RLY CPU 1212C, 1M is the common for inputs I0.0–I0.7 and is a separate, electrically isolated return from the CPU's logic ground.

Prerequisites

• Siemens S7-1200 CPU 1212C AC/DC/RLY (6ES7212-1BD30-0XB0 or later -0XB0/-0XB0 firmware revisions). HSC1 uses I0.0, I0.1, I0.2, I0.3 (clock A, clock B, Z/marker, external reset).
• Incremental rotary encoder with quadrature output, supply 4.75–40 VDC (TRD-N60-RZWD or equivalent: NPN open-collector / voltage output, 60 mm body, up to 5000 ppr base).
• 24 VDC encoder supply capable of sourcing the encoder's load current (TRD-N60 max 50 mA).
• Shielded, twisted-pair cable for the encoder run, with the shield bonded to ground at one end only (typically the PLC cabinet ground bar).
• STEP 7 Basic / TIA Portal V11 SP2 or later (V13, V15, V16, V17, V18 supported) for the HSC configuration dialog and CTRL_HSC instruction.
• Wire ferrule and screw driver, plus a short jumper (1.5 mm² or 14 AWG) from the PLC chassis/ground to the 1M terminal of the input bank.

Siemens S7-1200 HSC Hardware Capabilities

The S7-1200 HSC feature is implemented in the processor's onboard inputs; it is not an external module. Each CPU supports up to six HSC channels, but the number of available channels is governed by the input map of the specific CPU model. The CPU 1212C provides four usable HSC channels because it has only 14 integrated digital inputs (8 on input byte 0, 6 on input byte 1, plus AI).

Maximum guaranteed input frequency per the S7-1200 system manual, Chapter 4 "High-speed counters":

The TRD-N60-RZWD at 1000 ppr base produces 4000 quadrature edges per revolution in 4X mode (100 kHz / 25,000 rps for the 1212C ceiling). For higher pulse counts or higher shaft speeds the CPU 1212C becomes the bottleneck; select a CPU 1214C/1215C or a CPU 1217C with differential inputs, or add a separate HSC module such as the Allen-Bradley 1756-HSC or a Keyence KV-SSC02 (4 MHz single-phase, 16 MHz at 2-phase 4×) when the application demands more headroom.

Encoder Wiring: TRD-N60-RZWD to CPU 1212C

The TRD-N60-RZWD wire color code per the Koyo datasheet is:

Configuring HSC1 in TIA Portal V11+ for AB Quadrature 1X

In the TIA Portal project tree, open Devices & Networks, select the CPU 1212C, and from the right-side inspector navigate to Properties > General > High-speed counters (HSC). Expand the HSC1 node and configure the following parameters:

For higher physical resolution without changing the encoder, switch the operating phase to AB Quadrature 4X (4 edges per A/B cycle, 80 kHz max on 1212C). For a TRD-N60 at 1000 ppr, 4X yields 4000 counts per shaft revolution.

Programmatic Control: ID1000 and CTRL_HSC

The current HSC1 count is read from the input double-word ID1000. To reset, gate, or change the count value at runtime, use the CTRL_HSC instruction in the user program. CTRL_HSC is edge-triggered — set the EN input with a one-shot or a tag that becomes true for exactly one scan.

ST Example: Reset HSC1 to 0 on a discrete input

IF "Reset_HSC1_PB" THEN
  "HSC1_Ctrl".HSC := 1;              // HSC1
  "HSC1_Ctrl".DIR := FALSE;          // Count up after reset
  "HSC1_Ctrl".CV  := 0;              // New count value
  "HSC1_Ctrl".RV  := 0;              // No preset reference value
  "HSC1_Ctrl".PERIOD := FALSE;       // No period measurement reset
  "HSC1_Ctrl".NEW_CV := TRUE;        // Load new CV into HSC
  "HSC1".CTRL_HSC_DB("HSC1_Ctrl");   // Invoke
END_IF;

Ladder Example: Same Function

Polling the Count in a Cyclic OB

"HSC1_Count_Engineering" := DWORD_TO_DINT("HSC1".ID1000);
"HSC1_RPM" := ("HSC1_Count_Engineering" - "HSC1_Count_Prev") / "PPR_x4" * 60 / "Delta_t_s";
"HSC1_Count_Prev" := "HSC1_Count_Engineering";

Grounding and Noise Mitigation Procedure

1. Power down the PLC and the encoder supply. Verify zero energy with a meter on the 24 VDC rail.
2. Inspect the input bank. On a CPU 1212C AC/DC/RLY, the 1M terminal sits next to the I0.0–I0.7 group. Confirm whether a wire currently lands on 1M. If only the encoder's BLU and the encoder supply's (−) are connected, the 1M terminal may be left floating relative to the supply return.
3. Install a short, low-impedance jumper (1.5 mm² or 14 AWG, kept under 50 mm) from the PLC's chassis ground (the M5 ground stud on the bottom of the S7-1200) to the 1M terminal of the input bank. This is the documented step that solved the original failure.
4. Bond the encoder cable shield to the cabinet ground bar at the PLC end only. Do not bond the shield at the encoder end if the encoder body is itself isolated from the cabinet ground; double-grounded shields create ground loops.
5. Use a shielded, twisted-pair cable for the encoder run. Koyo recommends a 3-pair or 4-pair shielded cable for the TRD-N60 with 25 µm phase tolerance. The A/B pair should be a dedicated twisted pair; the Z and power pair should be separate.
6. Route the encoder cable at least 200 mm away from VFD output cables, motor power leads, and any unfiltered switching load. Cross perpendicular only when necessary.
7. Add a 24 V decoupling network at the PLC if the encoder shares the 24 V supply with a VFD or a large solenoid: a 0.1 µF ceramic in parallel with a 47 µF electrolytic, mounted at the PLC terminals, suppresses supply-borne noise that would otherwise couple through the encoder's output transistors into the input lines.
8. Power up. With the encoder stationary, watch ID1000 in the TIA Portal watch table. The value must be stable; a count that drifts ±1 with the shaft stopped indicates residual noise on A or B.

Verification and Commissioning Checks

1. Open the TIA Portal project, connect online to the CPU 1212C, and force a STOP-then-RUN transition to clear any latched HSC state.
2. Open the Watch table; add the tag ID1000 (DWord). With the encoder stationary, the value must hold constant. If it drifts, return to the noise-mitigation section.
3. Hand-turn the shaft exactly 5 revolutions clockwise. Record the count. Hand-turn 5 revolutions counter-clockwise. The count must return to the starting value within ±1 increment (the residual of the last partial quadrature transition).
4. Drive the shaft at the maximum application speed for at least 60 seconds. Watch ID1000 for undercount or overcount. If undercount appears at high speed only, the input filter is enabled — change it to "0.1 µs" or "0.0 µs" in the HSC properties. (A logic-level change of the filter in TIA Portal V15+ may require a re-compile and STOP-RUN-RUN transition of the CPU.)
5. Verify the Z (marker) function if used. With "Use Z input for homing" enabled in the HSC properties, rotate the shaft one full turn; on the Z pulse the count must reset to the configured initial value.
6. Add an HSC alarm (CV = RV or CV = limit) only if the application requires it; otherwise leave the limits at the DINT extremes to avoid unintended roll-overs.

Troubleshooting Matrix

Cross-Reference: Higher-Performance HSC Alternatives

If the application requires pulse rates above the 1212C ceiling, or if the encoder is differential (RS-422) and the S7-1200 single-ended inputs do not deliver adequate noise margin, consider an external HSC module:

• Allen-Bradley 1756-HSC / 1756-HSC/B ControlLogix module: 2 channels, 1 MHz differential inputs, integrated counter, period, and rate measurement with CIP Sync timestamp support. See the ControlLogix High-speed Counter Module User Manual (1756-UM007).
• Keyence KV-SSC02 high-speed counter unit for KV-series PLCs: 1 channel, 4 MHz single-phase or 16 MHz 2-phase 4×. See the KV-SSC02 product page.
• Siemens SM 1278 4HS / SM 1281 counter module for ET 200S / S7-1200 expansion: 4 high-speed counter channels at up to 200 kHz; requires the S7-1200 signal board or signal module interface.

For the TRD-N60-RZWD at 1000 ppr on a CPU 1212C, the practical mechanical speed ceiling in 4X quadrature is 80 000 / 4 000 = 20 rps = 1 200 rpm. The TRD-N60 is rated to 5 000 rpm maximum — when the application approaches that limit, the HSC will undercount and the encoder is the wrong choice or the PLC is the wrong choice. Always work the math before selecting components.