S7-1200 PID_Compact: Continuously Changing Setpoint Speed Sync

Synchronizing two gearmotors to run at matched speed is a classic follower / leader application. When the leader's speed reference is itself moving (for example because it tracks a process variable, a recipe ramp, a load profile, or a host PLC command), the follower's PID setpoint is no longer a static numeric value. It changes every PLC scan. This reference describes how to configure the SIMATIC S7-1200 PID_Compact block to accept a continuously changing setpoint derived from a master encoder or a master drive reference, and how to wire the slave feedback path so the closed loop regulates the speed error between the two gearmotors rather than chasing a fixed RPM target.

1. Application Overview and Control Objective

The application consists of two mechanically independent gearmotors that must rotate at matched speed. The leader (master) gearmotor carries an absolute or incremental encoder; the follower (slave) gearmotor carries a second encoder. The objective is for the slave to track the master's instantaneous speed closely enough that the position offset (integrated speed error) stays within a defined mechanical tolerance. Because the master speed itself varies with the host process, the setpoint supplied to the slave PID is non-constant and can change on every OB1 cycle.

Two architecturally valid approaches exist for this application. They are functionally different and produce different tuning results, different closed-loop bandwidth, and different commissioning effort.

1.1 Architecture A: Cascade / Mirror Setpoint

The master encoder is scaled to engineering units (RPM, percent, or mm/s) and written to the Setpoint input of the slave PID. The slave encoder is scaled to the same engineering units and written to the Input input. The PID computes Output to drive the slave inverter. The controller is in absolute speed control: it tries to make the slave speed equal to the master speed. The Setpoint tag is being rewritten every cycle by the application.

1.2 Architecture B: Speed-Error Outer Loop

The master speed reference (whether the encoder scaled value, or the analog command sent to the master drive) is also routed to the slave inverter as a feed-forward command. The PID Setpoint is fixed at 0.0. The PID Input is the algebraic difference (master speed - slave speed) from the two encoders. The PID Output is added to (or subtracted from) the master speed reference to produce the final slave drive command. The PID is acting as a synchronizing trim controller; it has a fixed setpoint of zero and the Setpoint tag does not need to change at all.

Architecture B is generally preferred when the goal is synchronization, because the controller is asked only to correct a small error, not to chase the full speed command. The derivative term is much easier to tune, the integral term is naturally bounded, and the response to a sudden setpoint change on the master is unaffected by the PID dynamics. The trade-off is that the slave drive must accept a speed command built from a base reference plus a trim signal, a feature most modern inverters support.

2. PID_Compact Block Identification and I/O Map

PID_Compact is the standard SIMATIC PID instruction shipped with TIA Portal. The block instance is created in the project tree under Technology > PID Control > PID_Compact, or by dragging PID_Compact from the Instructions task card. For S7-1200 firmware V4.x and later, the block is delivered as FB 1130, version 3.x (the exact block revision depends on the installed TIA Portal version). The instance DB exposes the following tags used in a speed-synchronization application.

The complete tag list and block identification are documented in the TIA Portal help under PID_Compact V1 / V2 / V3 for S7-1200. Refer to the TIA Portal V21 PID_Compact reference for the exact block revision delivered with a given TIA Portal install. See the official Siemens TIA Portal V21 documentation on PID parameters for the full parameter set, editability rules, and warnings about online parameter changes.

3. Wiring the Master Reference into the Setpoint

For Architecture A, the master encoder channel must be scaled to the same engineering units as the slave encoder channel. The two scaling blocks (NORM_X and SCALE_X in TIA Portal, or user-written FCs) must produce numerically identical full-scale values; otherwise the slave will deliberately run at a different speed than the master. A common commissioning error is to scale the master to RPM and the slave to percent, producing a 1.6x ratio that is not visible at standstill but becomes a permanent offset once the line runs.

Sample Structured Text (ST) that writes a master speed reference into the PID Setpoint tag every cycle:

// Master speed in RPM, already scaled from the master encoder
IF "HSC_Master".Status.Done THEN
    "DB_Master_Speed".RPM := "Scale_Master_Encoder"(
        NORM_X_OUT := "HSC_Master".CountValue
    );
END_IF;

// Feed master RPM into the slave PID setpoint every OB1
"Slave_PID_Compact".Setpoint := "DB_Master_Speed".RPM;

// Feed slave encoder back to the slave PID
IF "HSC_Slave".Status.Done THEN
    "Slave_PID_Compact".Input := "Scale_Slave_Encoder"(
        NORM_X_OUT := "HSC_Slave".CountValue
    );
END_IF;

Two engineering practices keep the Setpoint write clean:

1. Assign the master scaling function to a fixed-cycle OB (for example OB30) with a known period, and assign the same period to PID_Compact.Config.CycleTime. This guarantees the Setpoint is updated exactly once per PID execution.
2. Clamp the Setpoint value to SetpointLimit_L and SetpointLimit_H before it reaches the block. PID_Compact clamps internally, but pre-clamping prevents SetpointDisplay from showing transient noise outside the physical range on the HMI.

For an S7-1200 CPU 1214C DC/DC/DC (catalog 6ES7 214-1AG40-0XB0) or CPU 1215C, the onboard high-speed counters HSC1 through HSC6 support 24 V incremental encoders at up to 100 kHz (200 kHz on HSC1-HSC4 for differential signals). Wire each encoder's A, B, and Z (if used for homing) channels to the assigned inputs and configure the counter under Device configuration > Properties > Pulse generators (PTO/PWM) and counters. For analog output to the slave inverter, use an SM 1232 analog output module (e.g., 6ES7 232-4HD32-0XB0) or a signal board SB 1232 (6ES7 232-4HA30-0XB0) to provide a 0-10 V or 4-20 mA reference.

4. Cycle Time and Sampling Constraints

PID_Compact samples its inputs and computes its output at Config.CycleTime, which must be an integer multiple of the calling OB's cycle time. For a default S7-1200 OB1 cycle of 100 ms, set Config.CycleTime = 0.1 s. For a 10 ms cyclic interrupt OB (OB30 configured to 10 ms), set Config.CycleTime = 0.01 s.

For a gearmotor speed loop, the rule of thumb is that the PID sampling time should be at least 5x to 10x faster than the dominant mechanical time constant of the drive. A small gearmotor with inertia J, viscous friction B, and torque constant Kt on a current-controlled inverter has a mechanical time constant T_mech = J * R / (Kt * Kf) + J / B. For a typical 200 W gearmotor in the sub-500 W class, this constant is in the 30-200 ms range. A PID_Compact cycle of 10-20 ms is appropriate. For larger gearmotors (kW class), 20-50 ms is sufficient.

Working example: a 1024 PPR incremental encoder on a 3000 RPM gearmotor with a 10 ms PID cycle produces:

• Encoder frequency at full speed: f = 3000 / 60 * 1024 = 51,200 Hz
• Counts per PID cycle: N = 51,200 * 0.01 = 512 counts
• Minimum measurable speed change per cycle: 1 / 512 = 0.2% of full scale

This resolution is adequate for a percent-level speed control loop. For sub-percent accuracy, increase the PID cycle to 20 ms or upgrade the encoder to 2048 or 4096 PPR.

5. Pretuning, Fine Tuning, and the Continuously Changing Setpoint

The TIA Portal PID tuning wizard supports two automatic modes: pretuning (cold start) and fine tuning (warm start). The tuning algorithm intentionally applies step changes to the Setpoint to identify the process reaction curve. When the Setpoint is being written by application code on every cycle, the wizard cannot inject its own steps, and it will report a tuning fault (ErrorBits bit set, tuning aborted).

Recommended procedure:

1. Disconnect the Setpoint write from application code. Hold the Setpoint at a representative operating point (typically 50% of full speed).
2. Run PID_Compact pretuning by writing Mode = 1. The block walks the process through several step changes and populates Gain, TI, and TD with identified values.
3. Accept the computed parameters.
4. Switch the Setpoint write back to the master encoder feed. The PID is now operating on a moving setpoint with the gains identified at a single operating point.
5. For better tracking across the full speed range, run fine tuning (Mode = 2) at two additional operating points (e.g., 25% and 75% of full scale). PID_Compact averages the results into the Gain, TI, and TD tags.

If the application forbids holding the Setpoint stationary, alternative strategies exist:

• Run fine tuning only. Fine tuning tolerates small ongoing disturbances and adjusts the existing parameters rather than re-identifying the process from scratch.
• Run pretuning with the master drive stationary, then re-tune empirically in automatic mode by commanding known ramp profiles and observing response.

6. PI vs PID: Why the D-Term is Often Left Disabled

A derivative term computes the rate of change of the error. On a speed synchronization loop, the error itself is the rate of change of position. Differentiating it amplifies the noise already present in the encoder signal. A single bad encoder count from electrical noise produces a derivative spike large enough to saturate the output for one or more PID cycles, which then disturbs the slave drive unnecessarily.

Practical recommendations for a gearmotor sync loop:

1. Start with TD = 0.0 (D-term disabled) and tune Gain and TI for a critically damped response to a step disturbance.
2. If the response is too sluggish and a small amount of D-action would help, enable TD with a non-zero DerivativeDelay (typical 1-5 s for a 10 ms cycle, 5-20 s for a 100 ms cycle). DerivativeDelay applies a first-order low-pass to the D-term; larger values reduce derivative kick at the cost of D-term speed.
3. Cap the output slew rate. PID_Compact supports output scaling (Config.OutputScaling.UpperPointIn, UpperPointOut, LowerPointIn, LowerPointOut) but does not expose an explicit slew-rate limiter. If derivative-induced bumps are observed, slew-rate limit the Output_PER value in a downstream FB before it reaches the analog output module.

7. Output Limits, Anti-Windup, and Bumpless Transfer

When the manipulated variable hits an output limit (the inverter reaches its maximum speed reference) and the error persists, the integral term in a PI controller continues to accumulate. When the error finally reverses, the integrator must unwind before the controller responds. PID_Compact applies anti-windup automatically: it freezes the integrator when Output saturates and resumes accumulation only when Output comes back into the active range. No additional configuration is required for the standard anti-windup behavior.

The default output limits are 0.0% and 100.0% (Config.OutputScaling). For a bipolar drive (forward and reverse), change the lower point to -100.0%. The InputWarning_H and InputWarning_L tags are independent of output limits and can be set narrower to alarm the HMI if the process value approaches a physical limit.

Mode constants for PID_Compact:

For an application with a moving setpoint, the block should be placed in Mode = 3 (Automatic) for the duration of normal operation. Mode 4 (Manual) is used during commissioning only. Switching from Mode 4 to Mode 3 is bumpless: PID_Compact copies the current manual value into the integrator so the first automatic computation produces the same Output that the manual mode was producing.

When the application needs to gate the control (for example, interlock the slave drive to a safety chain), do not use Mode 0 unless the slave can coast to a stop safely. Prefer Mode 4 with ManualValue = 0 if a controlled zero hold is required, or use a hardwired enable input to the inverter and keep PID_Compact in Mode 3 with a Setpoint of zero so the integrator does not wind up.

8. Practical Commissioning Sequence

1. Wire the master encoder to a fast counter input (onboard or signal module). For S7-1200, HSC1-HSC6 are supported depending on the CPU. Confirm HSC configuration in the device configuration under Properties > Pulse generators and counters.
2. Wire the slave encoder to a second HSC.
3. Create two scaling FCs: one for the master, one for the slave. Verify that both produce the same engineering unit at the same physical RPM by commanding a known speed and reading both values in a watch table.
4. Insert a PID_Compact instance, assign it to OB30 (or OB1 if cycle greater or equal 100 ms is acceptable).
5. Configure SetpointLimit_L and SetpointLimit_H to the physical RPM range of the gearmotor (e.g., -3000 to +3000).
6. Configure InputWarning_L and InputWarning_H to alarm levels (e.g., plus or minus 5% of full scale).
7. Set Mode = 4 (Manual). Write ManualValue = 0. Verify the slave drive receives 0% reference.
8. Step ManualValue to 10%, 25%, 50% and verify the slave follows. Use this to confirm the polarity of Output and the direction of the drive. Reverse the sign of the output scaling if the direction is wrong.
9. Set Mode = 0 (Inactive). Apply the Setpoint write from application code and verify SetpointDisplay on the HMI matches the master speed reference.
10. Run pretuning (Mode = 1) at a fixed Setpoint, as described in Section 5.
11. Return Mode = 3 (Automatic). Verify the slave follows the master through a slow ramp, then through a step change in master speed.
12. Iterate Gain and TI for desired response: increase Gain until you see 5-10% overshoot on a step, then reduce by 30%. Reduce TI until the response is critically damped.

9. Verification Checklist

10. PID_Compact Error Bits (ErrorBits)

The ErrorBits tag is a DWord bitmask indicating diagnostic conditions. The exact bit assignment depends on the block version, but the canonical set for PID_Compact V2 / V3 is:

Bit names are illustrative; verify the exact mapping in the TIA Portal help for your block version. In production, monitor the bitmask and alarm on any non-zero bit.

11. Alternative Hardware Paths for Tighter Synchronization

For very tight synchronization requirements (printing, packaging, or material-handling lines where the integrated position error must stay below a few millimeters), PLC-based PID_Compact is usually not the right tool. The PLC scan period, the HSC update latency, and the analog output update latency together produce a closed-loop bandwidth that is rarely above 20-30 Hz, whereas a digital synchronization card operates at the inverter's current loop rate (typically 1-4 kHz).

11.1 SEW-Eurodrive DRS11B Synchronous Operation Card

SEW-Eurodrive offers the DRS11B Synchronous Operation Card for MOVIDRIVE B and MOVIFIT FC inverters. The card reads the master encoder signal and computes the slave speed command directly in the inverter firmware, with synchronization accuracy and encoder interface parameters defined in the manufacturer's datasheet. Refer to the official SEW DRS11B documentation for the exact accuracy class, encoder interface, parameter set, and wiring diagram.

11.2 ABB Frequency Input as Speed Reference

ABB ACS355, ACS580, and similar general-purpose drives accept a frequency input (typically 0-16000 Hz) as a speed reference. The master encoder can be wired directly to the slave drive's frequency input, bypassing the PLC entirely. The slave drive's own internal speed controller closes the loop on the slave encoder. This eliminates the PLC from the fast path and gives a closed-loop bandwidth limited only by the drive's current loop. It is the simplest solution for applications where the gearmotor pair must track a master reference with reasonable accuracy and the only adjustment needed is a small scale-factor trim.

Selection rule of thumb: tolerance of a few percent of speed, or position offset of a few centimeters at typical line speeds, is workable on the S7-1200 PID_Compact path. Tighter requirements warrant budgeting for a digital synchronization card from the inverter vendor.

12. Frequently Asked Questions