S7-1200 Seconds Counter in TIA Portal: Code and Troubleshooting

1. Why a Dedicated Seconds Counter on the S7-1200?

The S7-1200 CPU family (CPU 1211C, 1212C, 1214C, 1215C, 1217C) provides nanosecond resolution on its system clock, but the available time tags in the user program default to one of the following:

• DTL (Date_And_Time_Long): 12 bytes, year down to nanoseconds. Carries 8 ns of resolution but is awkward to increment by hand.
• Time IEC type: 32-bit signed milliseconds. Easy to use for timers, but reading "Time" inside OB1 gives the elapsed time of the last cycle, not wall-clock seconds.
• No native UDInt "SecondsSincePowerOn" tag on the S7-1200.

For runtime displays, batch timers and shift-hour counters you almost always want a plain UDInt or DInt that goes up by one each second. You then format that value to display in HMI tags. The four methods below all produce exactly that result; they differ in resource usage, determinism, and resilience to power cycles.

2. Method Comparison

3. Prerequisites and Clock Memory Byte Setup

For Methods 1 and 2 you must enable the clock memory byte in the CPU hardware configuration. Without it, the M-bit you reference will read FALSE forever — the most common reason the seconds counter never moves.

1. Open the TIA Portal project and select the S7-1200 CPU in the device tree.
2. Open Properties → System & Clock Memory.
3. Tick "Enable the use of clock memory byte".
4. Set the Address to the byte you want to use. The default is MB0. The discussion thread specifically called out the value 22 for a user who set the byte to MB22.
5. Click OK and download the hardware configuration to the PLC (not just the program — the entire device configuration must be reloaded for the change to take effect).

3.1 Default Bit Frequencies

Once the byte is enabled, each bit toggles at a fixed period. The periods below are the defaults shipped with every S7-1200 and S7-1500 CPU:

For a 1-second counter use bit .5. The original poster attempted M22.5, which is the correct bit — but only if byte 22 was actually configured as the clock memory byte.

4. Method 1: Clock Memory Byte with Edge Detection (LAD)

This is the most concise approach and is the one the discussion thread converged on. It uses a P_TRIG (rising-edge detector) to ensure the ADD only fires once per second rather than on every OB1 scan.

4.1 Tag Declaration

4.2 Network 1 — Counting

Network 1: Seconds counter via clock memory
%M22.5   "Clock_1Hz"
----| |---------|P TRIG|------(ADD_DI, 1, SecondCounter, SecondCounter)---

The contact %M22.5 closes every 0.5 s and opens every 0.5 s, producing a 50 % duty cycle at 1 Hz. P TRIG converts the closing edge into a single-cycle pulse, so the ADD fires exactly once per second. Using the closing edge (or the opening edge with N TRIG) avoids double-counting on a slow OB1.

4.3 Network 2 — Reset (Optional)

Network 2: Reset on operator command
%I0.0  "ResetSeconds"
----| |---------[MOVE, 0, SecondCounter]------------------

Add a reset input if HMI operators must zero the counter. Mark SecondCounter as Retain in the PLC tag table if the count should survive a power cycle.

5. Method 2: Multi-Instance TP_TIME Pulse Timer

Use this method when the clock memory byte is disabled, the byte is used by another subsystem, or you need a period that is not one of the eight standard frequencies. Siemens' official programming recommendation is to instantiate the IEC timer TP_TIME as a multi-instance inside a function block (FB). This keeps timer data encapsulated in the FB's Static section and avoids the need for a separate global DB.

1. In the project tree, add a new Function Block (e.g. FB_SecondsCounter).
2. In the FB interface, add a Static tag named Time_1 of type TP_TIME.
3. Add an Input tag Run of type BOOL.
4. Add a Static tag Counter of type DINT marked Retain.
5. Add an Output tag Seconds of type DINT.

5.1 FB Code

// FB_SecondsCounter
// Static
Time_1 : TP_TIME;     // IEC pulse timer, multi-instance
Counter : DINT;       // Retentive count

Network 1: 1 s pulse generator
%Run
----| |------[TP_TIME]---(Q := Pulse1Hz)----
                  |
                  +-- IN : Run
                  +-- PT : T#1s
                  +-- Q  : Pulse1Hz
                  +-- ET : unused

Network 2: Increment on rising edge of pulse
%Pulse1Hz
----| |---------|P TRIG|------(ADD_DI, 1, Counter, Counter)---

Network 3: Map to output
%Counter
----[MOVE, Counter, Seconds]---------------

Call the FB from OB1 in a cyclic instance DB. The pulse generator will produce a 1 s pulse on Pulse1Hz for the full second, which the rising edge will detect once per second and feed the ADD. Reference: Siemens TIA Portal Help — Using IEC timers and counters (S7-1200, S7-1500).

6. Method 3: Cyclic Interrupt OB Counter

The S7-1200 supports a hardware-driven cyclic interrupt OB (default name OB30 in TIA Portal, configurable interval 1 ms to 60 000 ms). Counting inside a cyclic OB isolates the increment from the OB1 jitter of the main program and guarantees that the counter ticks at exactly the configured interval regardless of the main scan time.

1. Right-click Program blocks in the device tree and choose Add new block → Organization block → Cyclic interrupt.
2. Name it OB_Cyclic_1s. TIA Portal assigns OB30 by default.
3. Open the OB's properties and set the Cycle time to 1000 ms.
4. Inside the OB, increment a global DINT tag SecondCounter by 1.

// OB_Cyclic_1s (OB30)
Network 1: Increment seconds counter on every cyclic call
[ADD_DI, 1, "SecondCounter", "SecondCounter"]

7. Method 4: RD_SYS_T / READ_CLK in OB1

If you need a seconds counter that is tied to wall-clock time (i.e. it survives a power cycle and is not driven by the clock memory), read the CPU real-time clock and compute the seconds since a reference value. The S7-1200 instruction is RD_SYS_T (in older projects READ_CLK). Output is a DTL structure.

// OB1
Network 1: Read current time
[RD_SYS_T] --> now_DTL

To produce a seconds counter, capture now_DTL on the first scan into start_DTL and compute diff_seconds = T_DIFF (now_DTL, start_DTL) / 1000 using the T_DIFF instruction (returns a TIME, which you divide by 1000 to get seconds). This approach is overkill for a simple counter but is the only one of the four that survives an OB1 cycle skip or a CPU stop without losing track of wall-clock time.

8. Complete Working Example for TIA Portal V11 / V15 / V17

The complete ladder snippet below compiles on TIA Portal V11 SP2 (the version the original poster used) and is forward-compatible with V15, V16, V17 and V18. It uses only standard IEC instructions and global PLC tags.

// PLC tags (default tag table)
"Clock_1Hz"   : BOOL   at %M0.5        // Clock memory byte bit 5
"SecCount"    : DINT   at %MD4  (Retain = TRUE)
"SecReset"    : BOOL   at %I0.0        // Reset pushbutton

// OB1
// Network 1: 1 s edge -> ADD
"Clock_1Hz"
----| |---------|P TRIG|------------(ADD_DI, IN1:=1, IN2:="SecCount", OUT:=>"SecCount")---

// Network 2: Reset on pushbutton (rising edge)
"SecReset"
----| |---------|P TRIG|------------[MOVE, IN:=0, OUT1:=>"SecCount"]----

Download the project (Hardware and Software) to the S7-1200. After a power cycle, the value of SecCount is restored from the retain area and continues counting from the previous value.

9. Troubleshooting Matrix

9.1 Memory-Overlap Diagnostic

To confirm whether the clock memory byte is being clobbered:

1. Open the project, right-click the CPU and select Cross-reference.
2. Filter on the address MB22 (or whatever byte is configured).
3. Any tag other than the implicit clock memory access that writes to MB22 is suspect. Either move the clock memory byte, or stop the conflicting write.

9.2 Firmware Compatibility

The clock memory byte is supported on every S7-1200 CPU firmware from V1.0 onwards. Firmware 2.2 (released in 2012) is more than capable. If the bit does not toggle after a fresh factory reset and re-download, the issue is the project download, not the firmware. Reference the S7-1200 system manual for the supported feature set on your specific CPU: Siemens Industry Online Support.

10. Verification and Commissioning Checklist

Before signing off the seconds counter as "done":

1. Add the counter to a watch table with a 1 s refresh and confirm the value increments by exactly 1 every second for at least 60 cycles.
2. Toggle the reset input and confirm the counter returns to 0 and resumes counting.
3. Power-cycle the PLC and confirm the counter either resets to 0 (non-retentive) or continues from the previous value (retentive) as the design specifies.
4. Bind the counter to an HMI tag and confirm the display updates in real time.
5. Use the cross-reference to confirm no other block writes to the clock memory byte.

11. FAQ