S7-200 DCF77 Time Sync and Weekly Scheduler Implementation

1. Application Overview

The Siemens S7-200 family does not ship with a built-in radio-clock decoder, a weekly timer function block, or a dedicated astronomical-time instruction. Anything beyond a one-shot TON/TOF pair must be built by the programmer. This article covers two related tasks on a CPU 224 (typical order number 6ES7 214-1BD23-0XB0, also valid for 221/222/224XP/226):

1. Decoding a 24 V DC level from an external DCF77 receiver into a 59-bit minute frame and using it to overwrite the PLC's real-time clock (RTC) with SET_RTC.
2. Using READ_RTC plus a 7-day schedule table in V-memory to drive an output between arbitrary on/off times (for example, "energize Q0.0 Monday through Friday from 10:00 to 10:15"), with optional date-specific overrides for holidays.

The approach uses only standard S7-200 instructions: BGN_ITIME/CAL_ITIME for interval timing, SHRB for the bit table, READ_RTC/SET_RTC for the clock, and a small scheduler subroutine driven from the main scan or from a timed interrupt attached to SMB34.

2. Prerequisites

3. DCF77 Frame Architecture and Bit Map

DCF77 is a 77.5 kHz amplitude-modulated long-wave signal broadcast by Deutsche Funkturm on behalf of the Physikalisch-Technische Bundesanstalt (PTB) from Mainflingen, Germany. Each minute is encoded as 59 amplitude-keyed 1-second intervals. The carrier is reduced by ~25% during the first 100 ms (logical 0) or 200 ms (logical 1) of every second; the remaining 800/700 ms is full carrier. The 60th second carries no reduction, which the decoder uses to detect a clean start-of-minute.

Encoding rules:

• Bits 0-14: miscellaneous (minute marker, civil warning bits, transmitter ID).
• Bit 15: call bit (antenna change-over), normally 0.
• Bit 16: A1 = announcement of upcoming DST change.
• Bits 17-24: minutes tens/ones (BCD, bits 21-24 unused/zero), P1 = even parity of bits 17-24.
• Bits 25-35: hours tens/ones (BCD, bits 29-35 unused/zero), P2 = even parity of bits 25-35.
• Bits 36-58: day-of-week (3 bits), day tens/ones (BCD, 6 bits), month tens/ones (BCD, 5 bits), year tens/ones (BCD, 8 bits), P3 = even parity of bits 36-58.
• Bit 59 is the start-of-minute separator (no pulse); the decoder uses the 2 s carrier gap to resynchronize.

4. Receiver Wiring and Signal Conditioning

Pin assignments for a CPU 224 with the standard 35 mm DIN-mounted terminal block:

For CPU 224, inputs 0.0-0.7 are type-1 24 V inputs. A 13-30 V level reads as "1", a -5 to +5 V level reads as "0". The level shifter must therefore convert the receiver's 5 V (or 3.3 V) logic into a 24 V signal that swings clean above 13 V during the carrier-reduction (or non-reduction) window. A simple 74HC14 hex inverter with a pull-up to 24 V and a 2N2222 open-collector driver is a proven arrangement.

5. Pulse Width Measurement in Micro/WIN

Two implementation paths are practical on the S7-200:

1. Cyclic scan with BGN_ITIME / CAL_ITIME: simplest, runs in the main OB1. Effective up to about 5-10 ms scan time before pulse-edge resolution suffers. For DCF77 (1 Hz nominal) this is more than enough.
2. Timed interrupt on SMB34 (1-255 ms): recommended if your scan time exceeds 50 ms or if you have other heavy logic. Sample the input at a fixed 10 ms cadence and reconstruct the high/low interval from the sample count.

The subroutine below measures the width of the active-high pulse on I0.0 and classifies it as bit 0 (100 ms) or bit 1 (200 ms). The third case, an interval greater than 1.5 s with no edge, signals the start-of-minute marker.

// Subroutine SBR_0: DCF77 pulse width to bit
// Inputs : I0.0 (DCF77 data, level = carrier present)
// Outputs: V100.0 (bit value 0 or 1), V102 (pulse width ms)
// Globals: VB101 = sample counter, VW103 = last edge timestamp

NETWORK 1    // Detect rising edge of I0.0
LD     I0.0
EU
CALL   SBR_MarkEdge    // store current 10 ms tick count in VW103

NETWORK 2    // Detect falling edge
LD     I0.0
ED
CALL   SBR_Classify    // VW103 -> pulse width VW104

NETWORK 3    // Classify pulse width: 0 if < 150 ms, 1 if 150-300 ms
LDW>=  VW104, 150
AW<   VW104, 300
S      V100.0, 1        // bit = 1

NETWORK 4
LDW<   VW104, 150
R      V100.0, 1        // bit = 0

NETWORK 5    // Start-of-minute: no edge for > 1500 ms
LDW>=  VW106, 1500      // VW106 = ms since last falling edge
S      M0.1, 1           // M0.1 = SOM (start of minute flag)

Tune the 150/300 ms thresholds empirically. PTB specifications allow ±10 ms jitter, so 100-150 ms maps to logical 0 and 180-300 ms maps to logical 1. Anything outside 100-300 ms should be discarded as noise rather than committed to the bit table.

6. Building the 59-Bit Frame Table

Allocate a 60-bit shift register in V-memory starting at V200.0. Use SHRB with a positive count of +59 so each new bit shifts toward the high-order end and bit 58 lands in V207.4 (V200 = bits 0-7, V201 = bits 8-15, ..., V207 = bits 56-59).

// SBR_Frame: shift one classified bit into the 59-bit table on every SOM
NETWORK 1    // Load V100.0 into the SHRB DATA input on every falling edge
LD     I0.0
ED
SHRB   V100.0, V200.0, +59   // shift in 1 bit, oldest bit at V200.0

NETWORK 2    // On start-of-minute, freeze the table for decoding
LD     M0.1            // SOM flag set in pulse-width section
EU
MOVB   59, VB210       // bit counter starts at 59
S      M0.2, 1         // M0.2 = decode enable

The bit map V200.0-V207.4 now holds one complete minute frame. Bit 0 (M = minute marker) is at V200.0; bit 58 (year ones) is at V207.2; bit 59 (always 0) is the implicit SOM separator. Note that the SHRB index for bit n is V(200 + n/8).bit(n%8).

7. Decoding Time and Date from BCD

The minute, hour, day-of-week, day, month, and year fields are BCD-packed across the relevant spans. The decoder below pulls each field into a byte, validates the digit ranges, and stores them in a temporary RTC image starting at VB220.

// SBR_Decode: run when M0.2 is set, freeze frame in V200.0..V207.4
NETWORK 1    // Minutes tens/ones (bits 17..24, valid bits 17..20 = tens, 21..24 = ones)
LD     M0.2
EU
CALL   SBR_BCD        // inputs: VW200 offset, returns byte in VB220
              // minute_tens = BCD(bit 17..19) ; minute_ones = BCD(bit 20..23)
MOVB   VB220, VB221   // minute byte

A practical decoder uses a small lookup table in a data block rather than 50+ ladder rungs. The block holds a precomputed 256-byte BCD-to-binary conversion or, more compactly, an 11-entry array mapping each 4-bit nibble to its binary value 0-9. Anything above 9 (illegal BCD) is rejected as a frame error and the new RTC write is suppressed for that minute.

8. Parity and Validation

Three even-parity bits protect the three spans. Implement parity with a simple XOR reduction over the bit range:

// Parity check (even parity: XOR of all data bits plus parity bit = 0)
NETWORK 1    // P1: bits 17..24, even parity
LD     M0.2
EU
CALL   SBR_Parity    // computes XOR of V(200+floor(n/8)).bit(n%8) for n=17..24
              // returns 0 in VB230 if parity is even, 1 if odd
AB=    VB230, 0
S      M0.3, 1       // P1 OK

9. Writing the S7-200 Real-Time Clock

On a clean frame (parity OK, BCD OK, day-of-week in 1-7, day in 1-31, month in 1-12), call SET_RTC with the decoded fields. The S7-200 RTC format expected by SET_RTC is a T-format byte: T followed by year, month, day, hour, minute, second, and a reserved zero byte (8 bytes total).

// SBR_SetRTC: write decoded time to PLC
NETWORK 1    // All three parity flags set?
LD     M0.3       // P1 OK
A      M0.4       // P2 OK
A      M0.5       // P3 OK
A      M0.6       // BCD OK
CALL   SBR_PackT  // build T-format buffer at VB250..VB257
SET_RTC VB250      // overwrite S7-200 RTC with decoded time

Important behaviors of SET_RTC on CPU 224:

• Writes are applied within one PLC scan; the new value is readable with READ_RTC on the next scan.
• The buffered clock accuracy is typically ±2 min/month at 25 °C, drifting to ±5 min/month at 0-55 °C. With DCF77 sync, the PLC will only accumulate at most a few minutes of drift between good frames.
• Day-of-week 1 = Sunday in DCF77; S7-200 internal READ_RTC also returns 1 = Sunday, so the value passes through unchanged.

10. Weekly Schedule Data Block

Place a 7-day schedule in a data block (DB1). Each day holds up to 8 on/off pairs. A pair is two bytes: on-time (HH:MM packed as 0xHHMM) and off-time (same format). The block also carries an enable mask, so any day can be globally disabled without erasing the entries.

For a schedule of "Monday through Friday, 10:00 to 10:15", set:

// DB1 initial values (Micro/WIN data block editor)
SchedEnable = 0x3E        // b1..b5 set: Mon..Fri
MonOn1   = 16#0A00        // 10:00
MonOff1  = 16#0A15        // 10:15
TueOn1   = 16#0A00
TueOff1  = 16#0A15
WedOn1   = 16#0A00
WedOff1  = 16#0A15
ThuOn1   = 16#0A00
ThuOff1  = 16#0A15
FriOn1   = 16#0A00
FriOff1  = 16#0A15

11. Date-Specific Schedule Override

To handle "every Monday, except holidays", reserve a second data block (DB2) for exception dates. The PLC reads the current day/month from READ_RTC, scans DB2 for a match, and if found uses the override schedule (or forces the output off for that day).

// SBR_Sched: main weekly scheduler, called once per minute from OB1
NETWORK 1    // Read current RTC into VW300..VW307
READ_RTC VW300          // T-format buffer: year, month, day, hour, min, sec, reserved

The weekly scheduler evaluates DB1 first, then checks DB2 for a same-month-day match. An exception with mode 0 or 1 overrides the weekly result; mode 2 reads an alternate on/off pair from DB3.

12. STEP 7 Micro/WIN on Windows 10/11

Micro/WIN V4.0 SP9 is the final release for the S7-200 line and was developed against Windows XP/7. On Windows 10 and Windows 11 several symptoms are common: F1 (context help) opens a blank window or returns "Help not found"; the programming software occasionally loses the PPI port after sleep; and large project uploads may fail on first attempt.

Workarounds that do not require an additional tool:

1. Install Micro/WIN to a non-default path (for example C:\S7200\) so that the help file path is short enough to register cleanly with the Windows help engine.
2. Launch Micro/WIN as administrator; this restores the F1 lookup into the local .chm file. Windows 10/11 block .chm content from UNC paths or from paths under Program Files without elevation.
3. Set the launch compatibility to Windows 7 via the executable's Properties > Compatibility tab.
4. If F1 still fails, use the bundled readme.chm directly: it contains the same instruction reference as the F1 lookup but is opened by Explorer and bypasses the broken help-engine integration.

13. Commissioning Procedure

1. Connect the receiver antenna away from switch-mode PSUs, VFDs, and fluorescent lamps. Aim for a clear line-of-sight to Frankfurt (Mainflingen) and at least 1-2 m of separation from any 24 V cable run.
2. Power up and verify the receiver LED blinks once per second. A clean blink = carrier present, no blink = carrier reduced (data 0 or 1) and a 2 s gap = start of minute.
3. Download the project to the CPU 224. Place a breakpoint or single-step on the falling-edge network in SBR_0 and confirm VW104 cycles through 100 and 200 within ±20 ms of the receiver LED.
4. Force M0.0 to enable decoding. Use a status table to monitor VB200..VB207: the bits should populate from the SOM marker (bit 0) upward to bit 58 over 59 seconds.
5. Use a watch table to call SBR_Decode and inspect VB220..VB226. Cross-check with a phone app that displays DCF77 frame decode live.
6. Confirm the three parity bits on three consecutive minutes. If parity is intermittently wrong, increase the 10 ms interrupt to 5 ms to improve edge resolution, or add a 200 ms blanking window after each edge to reject switch-bounce artefacts.
7. Force a known good frame and confirm SET_RTC updates the PLC clock. Power-cycle the PLC and confirm the clock retains the time (CPU 224 has a super-cap-backed RTC that holds for ~100 hours at 25 °C).
8. Activate the scheduler, set DB1 to a 1-minute test window ("fire the output for 60 seconds starting now"), and verify Q0.0 energizes at the second mark and drops at the off-time mark.
9. Run for 24 hours and log parity failures. A clean DCF77 signal at good reception should produce fewer than 2 bad frames per 24 hours.

14. Troubleshooting Matrix